;------------------------------------------------------------------------------
;  This file defines the Monitor Configuration Parameters
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 2001
;  Version 4.02
;------------------------------------------------------------------------------
;
; Definitions of Monitor Parameters
; ---------------------------------
;
; Define the monitor data and code area
; 
; Dieses Include ist je nach Target in den Unterverzeichnissen RAMINC oder FLASHINC
$INCLUDE(AREA.INC)
;
; VECTAB: Defines the Interrupt Vector Address relocation (used for the 
;         initialization of the VECSEG register).  You should locate interrupts
;         in your target application to the same address with uVision2 Project-Options
;         for Target-L166 Misc-Interrupt Vector Table Address (generates the L166 
;         VECTAB directive).
%DEFINE (VECTAB) (0000000H)    ; default Address 0
;
; BAUDRATE: Defines the communication Baudrate for NON-BOOTSTRAP Mode.
; Notes: For SIMULATED SERIAL MODE the max. Baudrate is 38400bps @20MHz Clock.
;        Use the default baudrate first, before you check higher baudrates.
;        This setting is not relevant when you are using BOOTSTRAP Mode.
;        You may set BAUDRATE to 0 to enable automatic baudrate detection.
;        Automatic baudrate detection does not work for the SIMULATED SERIAL MODE.
BAUDRATE     EQU   57600     ; default Baudrate is 9600 bps.
;
; CPU_CLOCK: Defines the internal CPU Clock frequency
; Notes: The internal Clock might be different from the XTAL frequency, due
;        to on-chip PLL.  This setting is not relevant for BOOTSTRAP Mode.
CPU_CLOCK    EQU   40000000 ; default clock for most chips is 20MHz
;
;------------------------------------------------------------------------------
; Definitions for Cpu Configuration Register CPUCON1
; ==================================================
;
; ZCJ: Zero Cycle Jump Function (CPUCON1.0):
_ZCJ     EQU    0       ; 0 = Disable Zero Cycle Jump Function
                        ; 1 = Enable Zero Cycle Jump Function
;
; BP: Branch Prediction Unit (CPUCON1.1):
_BP      EQU    0       ; 0 = Disable Branch Prediction Unit
                        ; 1 = Enable Branch Prediction Unit
;
; INTSCXT: Interruptability of Switch Context Instruction (CPUCON1.2):
_INTSCXT EQU    0       ; 0 = Disable Interruption of SCXT instruction
                        ; 1 = Enable Interruption of SCXT instruction
;
; SGTDIS: Disable Segmentation Control (CPUCON1.3):
$IF TINY
_SGTDIS  EQU    1       ; disable segmented mode for TINY model
$ELSE
_SGTDIS  EQU    0       ; enable segmented mode (Reset Value)
$ENDIF
;
; WDTCTL: Watchdog Timer Control (CPUCON1.4):
_WDTCTL  EQU    0       ; 0 = DISWDT executable until end of EINIT
                        ; 1 = DISWDT/ENWDT always executable
;
; VECSC: Vector Table Scaling Factor (CPUCON1.5 .. CPUCON1.6)
_VECSC   EQU    0       ; 0 = Space between two vectors is 2 words
                        ; 1 = Space between two vectors is 4 words
                        ; 2 = Space between two vectors is 8 words
                        ; 3 = Space between two vectors is 16 words
;
;
; Definitions for CPU Configuration Register CPUCON2
; ==================================================
;
; INIT_CPUCON2: Init CPUCON2 register
; --- Set INIT_CPUCON2 = 1 to initilize the SYSCON1 register
$SET (INIT_CPUCON2 = 0) ; default: do not initilize CPUCON2  
;
; SL: Short Loop Mode (CPUCON2.0)
_SL       EQU   1       ; 0 = Short Loop mode disabled
                        ; 1 = Short Loop mode enabled
;
; FASTPEC: Fast Pec Event Injection (CPUCON2.1)
_FASTPEC  EQU   1       ; 0 = Direct Injection of PEC Events disabled
                        ; 1 = Direct Injection of PEC Events enabled
;
; FASTBL: Fast Block Transfer Injection (CPUCON2.2)
_FASTBL   EQU   0       ; 0 = Direct Injection for Block Transfers disabled
                        ; 1 = Direct Injection for Block Transfers enabled
;
; RETST: Return Stack (CPUCON2.3)
_RETST    EQU   1       ; 0 = Return Stack disabled
                        ; 1 = Return Stack enabled
;
; OVRUN: Pipeline Bubble Overrun (CPUCON2.4)
_OVRUN    EQU   1       ; 0 = Overrun of Pipeline Bubbles not allowed
                        ; 1 = Overrun of Pipeline Bubbles allowed
;
; ZSC: Zero Cycle Jump Cache (CPUCON2.5)
_ZSC      EQU   1       ; 0 = Zero Cycle Jump Cache disabled
                        ; 1 = Zero Cycle Jump Cache enabled
;
; STEN: Stall Instruction (CPUCON2.6)
_STEN     EQU   0       ; 0 = Stall instruction disabled
                        ; 1 = Stall instruction enabled
;
; EIOIAEN: Early IO Injection Acknowledge
_EIOIAEN  EQU   1       ; 0 = Injection ack. by destructive read not guaranteed
;                       ; 1 = Injection ack. by destructive read guaranteed
; 
; BYPF: Fetch Bypass Control (CPUCON2.8)
_BYPF     EQU   1       ; 0 = Bypass Path from Fetch to Decode disabled
                        ; 1 = Bypass Path from Fetch to Decode enabled
;
; BYPPF: Prefecth Bypass Control (CPUCON2.9)
_BYPPF    EQU   1       ; 0 = Bypass Path from Prefetch to Decode disabled
                        ; 1 = Bypass Path from Prefetch to Decode enabled
;
; FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
_FIFOFED  EQU   3       ; 0 = FIFO disabled
                        ; 1 = FIFO filled with up to 1 instruction per cycle
                        ; 2 = FIFO filled with up to 2 instructions per cycle
                        ; 3 = FIFO filled with up to 3 instructions per cycle
;
; FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15)
_FIFODEPTH EQU  8       ; 0 = No FIFO entries (No FIFO)
                        ; 1 = 1 FIFO entry
                        ; ...
                        ; 8 = 8 FIFO entries
                        ; 9 - 15 = reserved
;
;
; Definitions for System Configuration Register SYSCON1
; =====================================================
;
; INIT_SYSCON1: Init SYSCON1 register
; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON3 register
$SET (INIT_SYSCON1 = 1)
;
; SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
_SLEEPCON EQU    0      ; 0 = Normal IDLE mode entered upone IDLE instruction
                        ; 1 = SLEEP mode entered upone IDLE instruction
                        ; 2 - 3 = reserved
;
; PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
_PDCFG    EQU    0      ; 0 = Port drivers are always ON (default)
                        ; 1 = Port drivers are off in IDLE or Sleep mode
                        ; 2 = Port drivers are off in Powerdown mode
                        ; 3 = reserved
;
; PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
_PFCFG    EQU    0      ; 0 = Program Flash is always ON (default)
                        ; 1 = Program Flash is off in IDLE or Sleep mode
                        ; 2 - 3 = reserved
;
; CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
_CPSYS    EQU    0      ; 0 = clock signal for CPU is PLL frequency
                        ; 1 = clock signal for CPU is PLL frequency / 2
                        ; 2 - 7 = reserved
;
;
; Definitions for System Configuration Register SYSCON3
; =====================================================
;
; INIT_SYSCON3: Init SYSCON3 register
; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
$SET (INIT_SYSCON3 = 1)
;
; SYSCON3:  Power Management (disable on-chip peripherals)
;
ADCDIS  EQU     0       ; 1 = disable Analog/Digital Converter    (SYSCON3.0)
ASC0DIS EQU     0       ; 1 = disable UART ASC0                   (SYSCON3.1)
SSC0DIS EQU     0       ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
GPTDIS  EQU     0       ; 1 = disable Timer Block GPT             (SYSCON3.3)
                        ; reserved                                (SYSCON3.4)
FMDIS   EQU     0       ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
CC1DIS  EQU     0       ; 1 = disable CAPCOM Unit 1               (SYSCON3.6)
CC2DIS  EQU     0       ; 1 = disable CAPCOM Unit 2               (SYSCON3.7)
CC6DIS  EQU     0       ; 1 = disable CAPCOM Unit 6               (SYSCON3.8)
                        ; reserved                                (SYSCON3.9)
ASC1DIS EQU     0       ; 1 = disable UART ASC1                   (SYSCON3.10)
I2CDIS  EQU     0       ; 1 = disable I2C Bus Module              (SYSCON3.11)
SDLMDIS EQU     0       ; 1 = disable SDLM (J1850) Module         (SYSCON3.12)
CANDIS  EQU     0       ; 1 = disable on-chip CAN Module          (SYSCON3.13)
                        ; reserved                                (SYSCON3.14)
SSC1DIS EQU     0       ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
;
;
;
; Definitions for Reset Configuration Register RSTCON
; ===================================================
;
; INIT_RSTCON: Init RSTCON register
; --- Set INIT_RSTCON = 1 to initilize the RSTCON register
$SET (INIT_RSTCON = 0)
;
; RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
_RSTLEN   EQU    0      ; 0 =   2 t_CPU clocks (default)
                        ; 1 =   4 t_CPU clocks
                        ; 2 =   8 t_CPU clocks
                        ; 3 =  16 t_CPU clocks
                        ; 4 =  32 t_CPU clocks
                        ; 5 =  64 t_CPU clocks
                        ; 6 = 128 t_CPU clocks
                        ; 7 = 256 t_CPU clocks
;
; RORMV: RSTOUT# Remove Control (RSTCON.4)
_RORMV    EQU    0      ; 0 = RSTOUT delievers RSTOUT# signal
                        ; 1 = RSTOUT pin operates as GPIO
;
; ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
_ROCOFF   EQU    0      ; 0 = RSTOUT is deactivated by user software
                        ; 1 = RSTOUT is deactiveted at end of reset
;
; ROCON: RSTOUT# Control Switch Off (RSTCON.6)
_ROCON    EQU    0      ; 0 = RSTOUT is activated upon any reset
                        ; 1 = RSTOUT is only activated upon a hardware reset
;
; RODIS: RSTOUT# Disable Control (RSTCON.7)
_RODIS    EQU    0      ; 0 = RSTOUT is controlled by other mechanism
                        ; 1 = RSTOUT is deactivated
;
;
;
; Definitions for PLL Control Register PLLCON
; ===========================================
;
; INIT_PLLCON: Init PLLCON register
; --- Set INIT_PLLCON = 1 to initilize the PLLCON register
$IF (NO_EA)
$SET (INIT_PLLCON = 1)
$ELSE
$SET (INIT_PLLCON = 0)
$ENDIF
;
; PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3)
_PLLODIV  EQU    4      ; 0 .. 14  Fpll = Fvco / (PLLODIV+1)
                        ; 15 = reserved
;
; PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5)
_PLLIDIV  EQU    0      ; 0 .. 3   Fin = Fosc / (PLLIDIV+1)
;
; PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
_PLLVB    EQU    2      ; ValueVCO output frequency    Base frequency
                        ; 0 = 100...150 MHz            20...80 MHz
                        ; 1 = 150...200 MHz            40...130 MHz
                        ; 2 = 200...250 MHz [def.]     60...180 MHz
                        ; 3 = (250...300 MHz) Reserved
;
; PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12)
_PLLMUL   EQU    24     ; 7 .. 31  Fvco = Fin * (PLLMUL+1)
                        ; 0 .. 6 = reserved
;
; PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
_PLLCTRL  EQU    3      ; 0 = Bypass PLL clock mult., the VCO is off
                        ; 1 = Bypass PLL clock mult., the VCO is running
                        ; 2 = VCO clock used, input clock switched off
                        ; 3 = VCO clock used, input clock connected
;
; PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
_PLLWRI   EQU    0      ; 0 = Register PLLCON may be written
                        ; 1 = Write cycles to register PLLCON are ignored
;
;
; Definitions for Frequency Output Signal FOCON
; =============================================
;
; INIT_FOCON: Init FOCON register
; --- Set INIT_FOCON = 1 to initilize the FOCON register
$SET (INIT_FOCON = 1)
;
; CLKEN: CLKOUT Enable (FOCON.7)
_CLKEN    EQU     1     ; 0 = P3.15 is IO pin when _FOUT is 0
                        ; 1 = P3.15 outputs signal CLKOUT
;
; FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13)
_FORV     EQU     0     ; is copied to FOCNT upon each underflow of FOCNT
;
; FOSS: Frequency Output Signal Select (FOCON.14)
_FOSS     EQU     0     ; 0 = Output of the toggle latch; 0.5 duty cycle
                        ; 1 = Output of reload counter; duty cycle depends on FORV
;
; FOEN: Frequency Output Enable (FOCON.15)
_FOEN     EQU     1     ; 0 = P3.15 is IO pin when _CLKEN is 0
                        ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
;
;
; ============= CONFIGURE EXTERNAL BUS (EBC) BEHAVIOUR =====================
;
; --- Set CONFIG_EBC = 1 to initialize the EBCMOD0/EBCMOD1 registers
$SET (CONFIG_EBC = 1)   ; 0 = EBCMOD0/EBCMOD1 are set during reset according the 
                        ;     of configuration bus (typical Port0) values.
                        ; 1 = the following external bus configuration values
                        ;      are written to EBCMOD and BUSACT0
;
; Definitions for EBC Mode 0 register EBCMOD0
; ===========================================
;
; SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3)
_SAPEN      EQU    4    ; 0 = No segment address pins enabled
                        ; 1 = One (A16) segment address pin enabled
                        ; : = :        
                        ; 8 = Eight (A16 .. A23) address pins enabled
                        ; 9 - 15 = reserved
;
; CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7)
_CSPEN      EQU    5    ; 0 = No CS pins enabled
                        ; 1 = One CS (CS0) pin enabled
                        ; : = :
                        ; 8 = Eight CS (CS0 .. CS7) pins enabled
                        ; 9 - 15 = reserved
; Note: the number of available CS pins depends on the chip used
;
; ARBEN: Bus Arbitration Pins Enabled (EBCMOD0.8)
_ARBEN      EQU    0    ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
                        ; 1 = HOLD, HLDA and BREQ pins act normally
;
; SLAVE: SLAVE mode enable (EBCMOD0.9)
_SLAVE      EQU    0    ; 0 = Bus arbiter acts in master mode
                        ; 1 = Bus arbiter acts in slave mode
;
; EBCDIS: EBC pins disable (EBCMOD0.10)
_EBCDIS     EQU    0    ; 0 = EBC is using the pins for external bus
                        ; 1 = EBC off (pins to be used as GPIO if implemented)
;
; WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
_WRCFG      EQU    1    ; 0 = Pins act as WR and BHE
                        ; 1 = Pins act as WRL and WRH
;
; BYTDIS: BHE pin disable (EBCMOD0.12)
_BYTDIS     EQU    0    ; 0 = BHE enabled
                        ; 1 = BHE disabled (GPIO function if implemented)
;
; ALEDIS: ALE pin disable (EBCMOD0.13)
_ALEDIS     EQU    0    ; 0 = ALE pin enabled
                        ; 1 = ALE pin disabled (GPIO function if implemented)
;
; RDYDIS: READY pin disable (EBCMOD0.14)
_RDYDIS     EQU    1    ; 0 = READY enabled
                        ; 1 = READY disabled (GPIO function if implemented)
;
; RDYPOL: READY pin polarity (EBCMOD0.15)
_RDYPOL     EQU    0    ; 0 = READY pin is active low
                        ; 1 = READY pin is active high
;