||          MV    .L2     B_Wptr_end,   B_Wptr                ; not coded||          MVK   .S1     0,            A_last_coeff          ;not coded 12Q4            AND   .D2     B_cbp_mask,   B_cbp,    B_coded     ; cbp||          MVK   .S2     126,          B_const126            ; const  [!B_coded]B     .S1     mismatch                            ; not coded||[!B_coded]ADD   .L2     B_outi,       B_const126, B_outi    ; not coded ; branch occurs 5 cycles later* ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== *        .asg            B31,        B_cnt_bk                          .asg            A31,        A_top0h_bk        .asg            A30,        A_top0l_bk        .asg            A28,        A_dc_prec        .asg            A25,        A_len                           .asg            A20,        A_const32        .asg            A29,        A_Mpeg2v        .asg            B30,        B_block        .asg            B0,         B_flag        .asg            B0,         B_12Q4              ; 12Q4 MERGE        .asg            B2,         B_cc        .asg            A1,         A_cc0        .asg            A0,         A_cc1        .asg            A2,         A_b        .asg            A0,         A_c        .asg            B30,        B_d1        .asg            A27,        A_dc_len        .asg            B1,         B_dc_size        .asg            B1,         B_non420_cc         ; 2 W-mat        .asg            B0,         B_d        .asg            B30,        B_dc_diff        .asg            A26,        A_r1        .asg            A9,         A_r2        .asg            A23,        A_half_range        .asg            B28,        B_r3        .asg            A2,         A_test0        .asg            B29,        B_r4        .asg            A16,        A_r5        .asg            A24,        A_pred        .asg            A28,        A_val        .asg            A27,        A_invq        .asg            A27,        A_valdq        .asg            A27,        A_lentot        .asg            A26,        A_lentot_c        .asg            A27,        A_r6h        .asg            A26,        A_r6l        .asg            A24,        A_r7        .asg            A25,        A_bptr2        .asg            B30,        B_bptr_cmpl1        .asg            A26,        A_r8        .asg            B30,        B_r9        .asg            A24,        A_t20        .asg            A27,        A_t9h        .asg            A26,        A_t9l        .asg            A27,        A_t8h        .asg            A26,        A_t8l        .asg            A25,        A_t30* ========================================================================= *        MV      .L1     A_word1_bk,  A_word1                    ;restore||      MV      .L2     B_word2_bk,  B_word2                    ;restore||      MV      .D2     B_bsbuf_circ_bk, B_bsbuf_circ           ;restore||      MV      .S1X    B_bptr_bk,   A_bptr                     ;restore||      MV      .S2     B_cnt,       B_cnt_bk                   ;preserve; B_cnt_bk shares its register with B_run_bk, in case of not coded MB; B_run_bk is always <65 (since B_cnt_bk is) which ensures that the fault; flag (B_err) is not set.          [B_coded]SUB  .S2     B_num_blocks, B_cnt,    B_block         ;2 W-mat ||    CMPGT     .L2     B_num_blocks, 6,        B_non420        ;2 W-mat  [B_coded]CMPLT.L2     B_block,    4,          B_flag          ;[ 3,0] ||[B_coded]ZERO .S2     B_cc                                    ;[ 3,0] ||[!B_coded]MVK .D2     1,          B_flag                      ; not coded||      SHRU    .S1     A_top0h_bk:A_top0l_bk,  8, A_empty:A_top0_bk ;[ 3,0] ||      XPND2   .M2     B_non420,   B_non420                    ; 2 W-mat  [!B_flag]AND  .S2     B_block,    1,          B_cc            ;[ 4,0] ||      LMBD    .L1     0,          A_top0_bk,  A_b             ;[ 4,0] ||      LDW     .D2T2   *+B_SP[9],  B_Wptr                      ;W-mat basadr  [!B_flag]ADD  .D2     B_cc,       1,          B_cc            ;[ 5,0] ||      ZERO    .L1     A_cc0                                   ;[ 5,0]         ADD     .D1     A_b,        1,          A_dc_len        ;[ 6,0] ||[!B_cc]CMPGT  .L1     A_b,        8,          A_cc0           ;[ 6,0]||[!B_cc]ADD    .D2X    A_b,        2,          B_dc_size       ;[ 6,0] ||[!B_cc]SHRU   .S1     A_b,        1,          A_b             ;[ 6,0] ; --- Branch occurs if MB not coded        SHRU    .S2X    A_top0_bk,  29,         B_d1            ;[ 7,0]   [!B_cc]SUB    .L2     B_d1,       4,          B_d             ;[ 8,0] ||      SHRU    .S1     A_top0_bk,  30,         A_c             ;[ 8,0] ||[ B_cc]ADD    .D2X    A_b,        1,          B_dc_size       ;[ 8,0] ||       MVK    .S2     128,        B_const128                  ; 2 W-mat  [ B_cc]MVK    .S2     1,          B_d                         ;[ 9,0] ||[!A_c]SUB     .L2     B_dc_size,  1,          B_dc_size       ;[ 9,0]         ZERO    .S1     A_cc1                                   ;[10,0] ||[!B_d]SUB     .D2     B_dc_size,  3,          B_dc_size       ;[10,0] ||[!A_b]ADD     .D1     A_dc_len,   1,          A_dc_len        ;[10,0]   [ B_cc]CMPGT  .L1     A_b,        9,          A_cc1           ;[11,0]||[ A_cc0]MVK   .L2     11,         B_dc_size                   ;[11,0] ||[ A_cc0]MVK   .D1     9,          A_dc_len                    ;[11,0]   [ A_cc1]MVK   .S2     11,         B_dc_size                   ;[12,0]||[ A_cc1]MVK   .S1     10,         A_dc_len                    ;[12,0]        SHL     .S1     A_top0_bk,  A_dc_len,   A_r1            ;[13,0]   [ B_dc_size]SUB.S1X   B_dc_size,  1,          A_r2            ;[14,0] ||[ B_dc_size]SUB.S2    B_const32,  B_dc_size,  B_r3            ;[14,0] ||      ZERO    .L2     B_dc_diff                               ;[14,0] ||      ADD     .D1X    A_dc_len,   B_dc_size,  A_lentot        ;[14,0]   [ B_dc_size]SHL.S1    A_const1,   A_r2,       A_half_range    ;[15,0] ||[ B_dc_size]SHRU.S2X  A_r1,       B_r3,       B_dc_diff       ;[15,0] ||      SUB     .L1X    B_const32,  A_lentot,   A_lentot_c      ;[15,0]         ZERO    .L1     A_test0                                 ;[16,0] ||      SHRU    .S1     A_top1,     A_lentot_c, A_r7            ;[16,0] ||      LDW     .D1T1   *+A_Mpeg2v[DCPREC_M2OFF],   A_dc_prec   ;param  [ B_dc_size]CMPLT.L1X B_dc_diff,  A_half_range,         A_test0    ;[17,0]||      SHL     .S1     A_top0h_bk:A_top0l_bk,  A_lentot, A_r6h:A_r6l;[17,0]||      ADD     .D1     A_bptr,     A_lentot,   A_bptr2         ;[17,0] ||      AND     .L2     B_non420,   B_cc,       B_non420_cc     ; 2 W-mat        LDW     .D2T1   *B_dc_pred[B_cc],       A_pred          ;[18,0] ||      ADD     .S1     A_r6l,      A_r7,       A_top0l_bk      ;[18,0] ||      MV      .D1     A_r6h,      A_top0h_bk                  ;[18,0] ||      CMPGT   .L1     A_bptr2,    A_const31,  A_test2         ;[18,0] ||[B_non420_cc]ADD.L2   B_Wptr,     B_const128, B_Wptr          ;if cc!=0 select 2nd W-mat; =============================== PROLOG ==============================  [ A_test0]SHL .S1     A_half_range,           1,          A_r5;[19,0] ||      NORM    .L1     A_top0h_bk:A_top0l_bk,  A_nrm           ;[19,0] ||      CMPGT   .L2X    A_const16,  1,          B_12Q4          ; 12Q4 MERGE  [ A_test0]ADD .L2     B_dc_diff,  1,          B_r4            ;[20,0] ||[ A_test2]LDW .D2T2   *B_bsbuf_circ++,        B_word2         ;[20,0] ||      MVK     .S1     36,         A_const36                   ;[20,0] ||      MPY     .M1     A_nrm,      -16,        A_t20           ;[20,0]   [ A_test0]SUB .D2X    B_r4,       A_r5,       B_dc_diff       ;[21,0] ||      SHL     .S1     A_top0h_bk:A_top0l_bk,  A_nrm, A_t9h:A_t9l;[21,0] ||[B_12Q4]SUB   .L1     A_dc_prec,  4,          A_dc_prec       ; 12Q4 MERGE        AND     .D1     A_bptr2,    A_const31,  A_bptr          ;[22,0] ||      SHRU    .S1     A_t9h:A_t9l,            A_const36, A_t8h:A_t8l;[22,0] ||      SUB     .L1     A_len_tbl_adr,          A_t20,      A_t30     ;[22,0]         SUB     .S1     3,          A_dc_prec,  A_invq          ;[23,0] ||      ADD     .L1X    A_pred,     B_dc_diff,  A_val           ;[23,0] ||      LDBU    .D1T1   *A_t30[A_t8l],          A_len           ;[23,0]         SHL     .S1     A_val,      A_invq,     A_valdq         ;[24,0] ||[ A_test2]MV  .D1X    B_word2,    A_word1                     ;[24,0] || [A_test2]MV  .L1     A_word1,    A_word1_rw                  ; RWD||      SUB     .D2X    B_const32,  A_bptr,     B_bptr_cmpl1    ;[24,0]         SHRU    .S1     A_top0h_bk:A_top0l_bk,  8, A_empty:A_top0_bk;[25,0] ||      SHRU    .S2     B_word2,    B_bptr_cmpl1,           B_r9;[25,0]         STH     .D2T1   A_valdq,    *B_outi                     ;[26,0] ||      SHL     .S1     A_word1,    A_bptr,     A_r8            ;[26,0]         STW     .D2T1   A_val,      *B_dc_pred[B_cc]            ;[27,0] ||      ADD     .L2X    B_sum,      A_valdq,    B_sum           ;[27,0] ||      MVK     .S1     32,         A_const32                   ;[27,0] ||      ADD     .L1X    A_r8,       B_r9,       A_top1          ;[27,0] ||      MV      .S2     B_cnt_bk,   B_cnt                       ;restore* ------------------------------------------------------------------------- *        SUB     .S2X    A_len,      5,          B_rld_left      ;[10,1] ||      CMPLT   .L2X    A_len,      5,          B_test3         ;[10,1] ||      ADD     .L1     A_bptr,     A_len,      A_bptr1         ;[10,1] ||      SHL     .S1     A_top0h_bk:A_top0l_bk,  A_len, A_ptop0h:A_ptop0l;[10,1] ||      SUB     .D1     A_const32,  A_len,      A_len_c         ;[10,1]   [B_test3]MPY  .M2     B_rld_left, 0,          B_rld_left      ;[11,1] ||      MV      .L2X    A_top0_bk,  B_top0_bk                   ;[11,1] ||      AND     .S1     A_const31,  A_bptr1,    A_bptr          ;[11,1] ||      MV      .D1     A_ptop0h,   A_top0h                     ;[11,1] ||      NORM    .L1     A_ptop0h:A_ptop0l,      A_nrm           ;[ 1,2]        CMPGT   .L1     A_bptr1,    A_const31,  A_test2         ;[12,1] ||      MPY     .M1     A_nrm,      -16,        A_t2            ;[ 2,2] ||      SHL     .S1     A_ptop0h:A_ptop0l, A_nrm, A_t1h:A_t1l   ;[ 2,2] ||      MVK     .S2     126,         B_const126                 ;const        SHL     .S2     B_top0_bk,  B_rld_left, B_t13           ;[13,1] ||      MPY     .M2X    B_const32,  A_len,      B_t12           ;[13,1]         SHRU    .S2     B_t13,      27,         B_t14           ;[14,1] ||[ A_test2]LDW .D2T2   *B_bsbuf_circ++,        B_word2         ;[14,1] ||      SHRU    .S1     A_t1h:A_t1l, A_const36, A_t4h:A_t4l     ;[ 4,2] ||      SUB     .L1     A_len_tbl_adr,          A_t2,       A_t3;[ 4,2]         ADD     .L2     B_t14,      B_t12,      B_t15           ;[15,1]||      SUB     .S2X    B_const32,  A_bptr,     B_bptr_cmpl     ;[15,1] ||[ A_test2]MV  .L1X    B_word2,    A_word1                     ;[15,1] || [A_test2]MV  .S1     A_word1,    A_word1_rw                  ; RWD||      LDBU    .D1T1   *A_t3[A_t4l],           A_len           ;[ 5,2]         ADD     .L2     B_t15,      B_t15,      B_t16           ;[16,1] ||      SUB     .D1     A_len,      24,         A_test1         ;[16,1] ||      SHRU    .S1     A_top1,     A_len_c,    A_t7            ;[16,1]   [ A_test1]LDB .D2T2   *B_rld_table_adr[B_t16],B_level         ;[17,1] ||      ADD     .D1     A_ptop0l,   A_t7,       A_top0l         ;[17,1] ||      ADD     .L2     B_rld_table_adr,     1, B_rld_table_adr_1;const  [ A_test1]LDB .D2T2   *B_rld_table_adr_1[B_t16], B_run        ;[18,1] ||      EXT     .S2     B_top0_bk,  12, 20,    B_level          ;[18,1] ||      SHRU    .S1     A_top0h:A_top0l, 8,    A_empty:A_top0_bk;[ 8,2]         SHRU    .S2     B_word2,    B_bptr_cmpl,B_t9            ;[19,1] ||      SHL     .S1     A_word1,    A_bptr,     A_t8            ;[19,1] ||      ADD     .L2     B_Wptr,     B_const126, B_Wptr_end      ;rset 2 W-mat||      MV      .L1     A_top0h:A_top0l, A_top0h_bk:A_top0l_bk  ;preserve||      MPY     .M2X    1,          A_bptr,     B_bptr_bk       ;preserve||      LDW     .D1T1    *+A_Mpeg2v[QSCL_M2OFF],A_qscl        SUB     .S2X    A_len,      5,          B_rld_left      ;[10,2] ||      CMPLT   .L2X    A_len,      5,          B_test3         ;[10,2]||      ADD     .L1     A_bptr,     A_len,      A_bptr1         ;[10,2] ||      SHL     .S1     A_top0h:A_top0l, A_len, A_ptop0h:A_ptop0l;[10,2]