.asg            B9,         B_t16        .asg            A11,        A_outi      ; 12Q4           .asg            A12,        A_cnum      ; 12Q4        .asg            A13,        A_const16   ; 12Q4        .asg            B18,        B_constFFF0 ; 12Q4  * ========================================================================= *        .sect ".text:hand"        .global _mpeg2_vld_inter_asm        .global _IMG_len_tbl0         .global _IMG_rld_table0; Mpeg2v structure:BSBUF_M2OFF      .set   0x0NEXTWPTR_M2OFF   .set   0x1BPTR_M2OFF       .set   0x2WORD1_M2OFF      .set   0x3WORD2_M2OFF      .set   0x4TOP0_M2OFF       .set   0x5TOP1_M2OFF       .set   0x6ZPTR_M2OFF       .set   0x7QSCL_M2OFF       .set   0x9CBP_M2OFF        .set   0xBFAULT_M2OFF      .set   0xC_mpeg2_vld_inter_asm:; parameters: B_Wptr, B_outi, A_Mpeg2v, B_12Q4, A_num_blocks, B_bsbuf_words;             A4,     B4,     A6,       B6,     A8,           B8* ========================================================================= **  Setup* ========================================================================= *        .asg            B15,        B_SP        ; Stack pointer, B datapath        .asg            A16,        A_SP        ; Stack pointer, A datapath        .asg            B0,         B_csr       ; CSR's value        .asg            B1,         B_no_gie    ; CSR w/ GIE bit cleared        .asg            B3,         B_ret       ; Return address        .asg            A29,        A_Mpeg2v        .asg            B18,        B_Mpeg2v        .asg            B2,         B_cnt        .asg            A10,        A_amr_arg            ; AMR arg        .asg            B9,         B_amr_arg            ; AMR arg        STW     .D2T1   A10,        *B_SP--[9]           ; RWD, MERGE, 2 W-mat||      MVC     .S2     CSR,        B_csr                ; Get CSR's state||      MV      .L2     B4,         B_outi  ||      MV      .L1     A6,         A_Mpeg2v||      MV      .S1X    B8,         A_amr_arg            ; AMR arg        STW     .D2T2   B_csr,      *+B_SP[1]            ; Save CSR||      AND     .L2     B_csr,      -2,         B_no_gie ; Clear GIE||      MV      .S2X    A4,         B_Wptr  ||      MV      .D1X    B_SP,       A_SP                 ; 12Q4 MERGE||      LMBD    .L1     1,          A_amr_arg,  A_amr_arg; AMR arg||      MVK     .S1     32,         A_const32            ; AMR arg        STW     .D2T2   B_ret,      *+B_SP[2]            ; Save return addr.||      STW     .D1T1   A14,        *+A_SP[6]            ; MERGE||      MV      .L2X    A6,         B_Mpeg2v||      MVC     .S2     B_no_gie,   CSR                  ; Disable ints.||      SUB     .L1     A_const32,  A_amr_arg,  A_amr_arg; AMR arg; ===== Interrupts masked here =====  * ========================================================================= **  Get bitstream info*  Setup circuar bitstream buffer*  Load table addresses and constants*  Block loop setup* ========================================================================= *        .asg     B31,    B_bsbuf        .asg     B29,    B_next_wptr         .asg     B27,    B_cbp        .asg     B0,     B0_amr_config        .asg     A21,    A_const1        .asg     A9,     A_tbs1        .asg     A4,     A_tbs2        .asg     B17,    B_tbs3        .asg     B3,     B_const126        .asg     B3,     B_const128        .asg     A14,    A_constSHR                             ; 12Q4 MERGE        LDW     .D2T2    *+B_Mpeg2v[BSBUF_M2OFF],      B_bsbuf||      LDW     .D1T1    *+A_Mpeg2v[TOP0_M2OFF],       A_top0_bk ||      MVK     .S2      128,          B_const128           ||      MV      .L2      B6,           B_12Q4                   ; 12Q4 MERGE        LDW     .D2T2    *+B_Mpeg2v[NEXTWPTR_M2OFF],   B_next_wptr||      LDW     .D1T1    *+A_Mpeg2v[TOP1_M2OFF],       A_top1 ||      ADD     .L2      B_Wptr,       B_const128,     B_Wptr_end||[!B_12Q4]MVK  .S1      20,           A_constSHR             ; non-12Q4 MERGE||      SHL     .S2X     A_amr_arg,    16,             B_amr_arg; AMR arg            LDW     .D1T1    *+A_Mpeg2v[BPTR_M2OFF],       A_bptr||      STW     .D2T2    B_Wptr,         *+B_SP[7]              ; 2 W-mat||      MV      .L2X     A8,             B_cnt                  ; 2 W-mat||      SET     .S2      B_amr_arg, 14, 14,     B_amr_arg          ; AMR arg            LDW     .D1T1    *+A_Mpeg2v[WORD1_M2OFF],      A_word1||      LDW     .D2T2    *+B_Mpeg2v[WORD2_M2OFF],      B_word2||      MVC     .S2      B_amr_arg,            AMR                 ; AMR arg||      MVK     .S1      31,            A_const31            LDW     .D1T1    *+A_Mpeg2v[QSCL_M2OFF],       A_qscl||      LDW     .D2T2    *+B_Mpeg2v[CBP_M2OFF],        B_cbp||[B_12Q4]MVK   .S1      16,           A_constSHR               ; 12Q4 MERGE; B_constFFF0 and B_Mpeg2v share the same register* ========================================================================= **  Setup bitstream pointers: top0h:top0l, top1 contain top bitstream* ========================================================================= *        .asg    B25,    B_word2_bk                       .asg    A28,    A_word1_bk                      .asg    A10,    A_word1_rw      ; RWD        .asg    A21,    A_word1_rw_bk   ; RWD        .asg    A31,    A_top0h_bk                       .asg    A30,    A_top0l_bk                       .asg    B28,    B_bptr_bk                      .asg    B30,    B_bsbuf_circ_bk        SHL     .S1      A_top0_bk,     8,          A_tbs1||      STW     .D2T1    A11,           *+B_SP[3]                   ||[B_12Q4]MVKL  .S2      0xFFF0,        B_constFFF0            ; 12Q4 MERGE           SHRU    .S1      A_top1,        24,         A_tbs2||      STW     .D2T1    A12,           *+B_SP[4]                    ||[!B_12Q4]MVKL .S2      0xFFFF,        B_constFFF0           ; non-12Q4 MERGE                ADD     .L1      A_tbs1,        A_tbs2,     A_top0l_bk||      ADD     .S1      A_bptr,        8,          A_bptr1||      STW     .D2T1    A13,           *+B_SP[5]                                     CMPGT   .L1      A_bptr1,       A_const31,  A_test2||      AND     .S1      A_bptr1,       A_const31,  A_bptr||      MVK     .S2      32,            B_const32||      ADDAW   .D2      B_bsbuf,       B_next_wptr,B_bsbuf_circ                [A_test2]MV   .S1      A_word1,                   A_word1_rw  ; RWD||[A_test2]MV   .L1X     B_word2,                   A_word1||[A_test2]LDW  .D2T2    *B_bsbuf_circ++,           B_word2||      SUB     .S2      B_const32,     A_bptr,     B_bptr_cmpl        MVKL    .S1      _IMG_len_tbl0,     A_len_tbl_adr ||      MVKL    .S2      _IMG_rld_table0,   B_rld_table_adr||      MV      .L2X     A_bptr,        B_bptr_bk||      STW     .D2T2    B_cnt,         *+B_SP[8]               ; 2 W-mat        MVKH    .S1      _IMG_len_tbl0,     A_len_tbl_adr||      MVKH    .S2      _IMG_rld_table0,   B_rld_table_adr         [B_12Q4]MVK   .S1      16,            A_const16               ; 12Q4 [!B_12Q4]MVK   .S1      1,             A_const16              ; non-12Q4                SHL     .S1      A_word1,       A_bptr,     A_tbs1||      SHRU    .S2      B_word2,       B_bptr_cmpl,B_tbs3                    ADD     .L1X     A_tbs1,        B_tbs3,     A_top1       ||      SHRU    .S1      A_top0_bk,     24,         A_top0h_bk||      MV      .D1      A_word1,       A_word1_bk||      MV      .D2      B_word2,       B_word2_bk||      MV      .L2      B_bsbuf_circ,  B_bsbuf_circ_bkblock_loop:* ------------------------------------------------------------------------- **  check cbp, etc.* ------------------------------------------------------------------------- *        .asg     B17,     B_cbp_mask        .asg     B0,      B_coded          .asg     A5,      A_last_coeff        .asg     A2,      A2_odd           .asg    B31,      B_run_bk        .asg    B26,      B_num_blocks                        ; 2 W-mat            SUB   .S2     B_cnt,        1,        B_cnt       ; cbp, cnt--||          ZERO  .L2     B_sum||          ZERO  .D2     B_run_bk                            ; not coded||          ZERO  .L1     A2_odd                              ; not coded||          MVK   .S1     1,            A_const1              ; cbp            SHL   .S2X    A_const1,     B_cnt,    B_cbp_mask  ; cbp||          MV    .L2     B_Wptr_end,   B_Wptr                ; not coded||          MVK   .S1     0,            A_last_coeff          ; not coded            AND   .D2     B_cbp_mask,   B_cbp,    B_coded     ; cbp||          MVK   .S2     126,          B_const126            ; const  [!B_coded]B     .S1     mismatch                            ; not coded||[!B_coded]ADD   .L2     B_outi,       B_const126, B_outi    ; not coded||[B_coded]LDW  .D2T2   *+B_SP[8],      B_num_blocks          ; 2 W-mat * =========================== PIPE LOOP PROLOG ============================ *        .asg     A0,      A_tm        .asg     B0,      B_tm_neg; the added lines below calculate cc which is required for weighting; matrix selection in 4:2:2 and 4:4:4 mode; the following additional registers are required: B_block, B_flag, B_cc        .asg    B31,      B_block         .asg    B1,       B_cc            .asg    B0,       B_flag          NORM    .L1     A_top0h_bk:A_top0l_bk,  A_nrm           ;[ 1,1] ||      SHRU    .S1     A_top0h_bk,     7,      A_tm            ;table mod        MPY     .M1     A_nrm,      -16,        A_t2            ;[ 2,1] ||      SHL     .S1     A_top0h_bk:A_top0l_bk,  A_nrm, A_t1h:A_t1l;[ 2,1]         MVK     .S1     36,             A_const36               ;const        SHRU    .S1     A_t1h:A_t1l,    A_const36,  A_t4h:A_t4l ;[ 4,1]||      SUB     .L1     A_len_tbl_adr,  A_t2,       A_t3        ;[ 4,1] ||[B_coded]LDW  .D2T2   *+B_SP[7],      B_Wptr             ;get W-mat base adr  [!A_tm]LDBU   .D1T1   *A_t3[A_t4l],   A_len                   ;[ 5,1]||[B_coded] SUB .L2     B_num_blocks,   1,          B_num_blocks;2 W-mat; branch occurs if not coded MB        SUB     .S2     B_num_blocks,   B_cnt,      B_block    ;cc for 2 W-mat||      CMPGT   .L2     B_num_blocks,   6,          B_flag     ;prevent 2 W-mat if 4:2:0        SHRU    .S1     A_top0h_bk:A_top0l_bk, 8, A_empty:A_top0_bk;[ 8,1] ||[B_flag]CMPGT .L2     B_block,        3,          B_flag     ;cc for 2 W-mat||      ZERO    .S2     B_cc                                   ;cc for 2 W-mat   [A_tm]MVK     .L1     2,          A_len                      ;table mod||[B_flag] AND  .D2     B_block,        1,          B_cc       ;cc for 2 W-mat          MV      .L1X    B_bptr_bk,  A_bptr                     ;restore||      MVK     .S2     128,         B_const128                ;const||[B_flag] ADD  .D2     B_cc,           1,          B_cc       ;cc for 2 W-mat            SUB     .S2X    A_len,      5,          B_rld_left      ;[10,1] ||      CMPLT   .L2X    A_len,      5,          B_test3         ;[10,1] ||      ADD     .L1     A_bptr,     A_len,      A_bptr1         ;[10,1] ||      SHL     .S1     A_top0h_bk:A_top0l_bk,  A_len, A_ptop0h:A_ptop0l;[10,1] ||[!A_tm]SUB    .D1     A_const32,  A_len,      A_len_c         ;[10,1] ||[B_cc]ADD     .D2     B_Wptr,     B_const128, B_Wptr          ;if cc!=0 select 2nd W-mat  [B_test3]MPY  .M2     B_rld_left, 0,          B_rld_left      ;[11,1] ||      MV      .L2X    A_top0_bk,  B_top0_bk                   ;[11,1] ||      AND     .S1     A_const31,  A_bptr1,    A_bptr          ;[11,1] ||      MV      .D1     A_ptop0h,   A_top0h                     ;[11,1] ||      NORM    .L1     A_ptop0h:A_ptop0l,      A_nrm           ;[ 1,2]         CMPGT   .L1     A_bptr1,    A_const31,  A_test2         ;[12,1] ||      MPY     .M1     A_nrm,      -16,        A_t2            ;[ 2,2] ||      SHL     .S1     A_ptop0h:A_ptop0l, A_nrm, A_t1h:A_t1l   ;[ 2,2] ||      ADD     .L2     B_Wptr,      B_const128, B_Wptr_end     ;reset        SHL     .S2     B_top0_bk,  B_rld_left, B_t13           ;[13,1]||      MPY     .M2X    B_const32,  A_len,      B_t12           ;[13,1] ||[A_tm]MVK     .S1     30,                     A_len_c         ;table mod||      MV      .L1     A_word1_bk,  A_word1                    ;restore||      MV      .L2     B_word2_bk,  B_word2                    ;restore||      MV      .D2     B_bsbuf_circ_bk, B_bsbuf_circ           ;restore        SHRU    .S2     B_t13,      27,         B_t14           ;[14,1]