#define DPU_BASE 0xb8000000
#define LCD_CLOCK_BASE (DPU_BASE+0x1040)
#define ALT_SIGNAL_BASE (DPU_BASE+0x1048)
#define SIGNAL_POLARRITY_BASE (DPU_BASE+0x104C)
#define HSYNC_TIME1_BASE (DPU_BASE+0x1050)
#define HSYNC_TIME2_BASE (DPU_BASE+0x1054)
#define VSYNC_TIME1_BASE (DPU_BASE+0x1058)
#define VSYNC_TIME2_BASE (DPU_BASE+0x105C)

#define INTERRUPTS_BASE (DPU_BASE+0x0000)
#define INTERRUPT_MASK_BASE (DPU_BASE+0x0004) 
#define DISPLAY_MODE_BASE (DPU_BASE+0x0008)
#define DISPLAY_SIZE_BASE (DPU_BASE+0x000c)
#define DISPLAY_CONTROL (DPU_BASE+0x100)
#define MAX_VIDEO_MEM_FETCH_LENGTH (DPU_BASE+0x0014)
#define TWOD_SCREEN_MODE (DPU_BASE+0x104)
#define PRO_ROW_HEIGHT (DPU_BASE+0x0108)
#define VIDEO_WINDOW_ORIGN (DPU_BASE+0x0138)
#define VIDEO_WINDOW_END (DPU_BASE+0x013C)
#define VIDEO_SCR_ADDRESS_Y (DPU_BASE+0x0164)
#define VIDEO_SCR_ADDRESS_CB (DPU_BASE+0x0168)
#define VIDEO_SCR_ADDRESS_CR (DPU_BASE+0x016C)

#define DEVICE_CONFIGURATION 0x900A0004
#define GPIO_BASE 0x900D0000
#define GPIO_DIRECTION1 (GPIO_BASE+0x0010)
#define GPIO_DIRECTION2 (GPIO_BASE+0x0050)
#define GPIO_DIRECTION3 (GPIO_BASE+0x0090)

#define GPU_BASE 0xA8000000
//GPU registers
#define GLE_SS_OFF              (0x00)
#define GLE_INT_OFF             (0x10)
#define GLE_CAUSE_OFF           (0x14)
#define GLE_DATA_RET_STATUS_OFF (0x40)

#define REN_INTR_OFF            (0x8c)
#define REN_VRAM1_XY_OFF        (0x90)
#define REN_VRAM2_XY_OFF        (0x94)
#define REN_SYSMEM_OFS_OFF      (0x98)
#define REN_PERF_CTR_OFF        (0xa4)

#define GLE_SS_REG              (GPU_BASE + GLE_SS_OFF             )
#define GLE_INT_REG             (GPU_BASE + GLE_INT_OFF            )
#define GLE_CAUSE_REG           (GPU_BASE + GLE_CAUSE_OFF          )
#define GLE_DATA_RET_STATUS_REG (GPU_BASE + GLE_DATA_RET_STATUS_OFF)
#define REN_INTR_REG            (GPU_BASE + REN_INTR_OFF           )
#define REN_PERF_CTR_REG        (GPU_BASE + REN_PERF_CTR_OFF       )
#define REN_VRAM1_XY_REG        (GPU_BASE + REN_VRAM1_XY_OFF       )
#define REN_VRAM2_XY_REG        (GPU_BASE + REN_VRAM2_XY_OFF       )
#define REN_SYSMEM_OFS_REG      (GPU_BASE + REN_SYSMEM_OFS_OFF     )
#define ADDR_SYSTEM_MEMORY_OFFSET (0x10008000)
#define pod(a,d)	(*(volatile unsigned *)a = d)