// system
#include "std_maiko_io.h"
#include "main.h"
#include "lcd.h"

void init_LCD();
void init_DPU();
void init_gpu();
void color_bar();

/*?乕僓偺僼僢僋娭?*/
void usr_int()
{
 
}

asm("
	.globl	_irq

_irq:

	/* ?僕僗僞戅旔 */
	STMFD	r13!,{r0-r12,r14}
	/* SPSR save*/
	/* SPSR 傪僙乕僽偡傞傑偱僽?乕僋嬛巭 */
	MRS	r0,spsr
	STMFD	r13!,{r0}
	bl	usr_int	/* ?傝?傒??僾?僌?? */

	/* SPSR ?婣丂偙偙偐傜僽?乕僋傗僗僥僢僾嬛巭 */
	LDMFD	r13!,{r0}
	MSR	spsr,r0

	/* ?僕僗僞?婣 */
	LDMFD	r13!,{r0-r12,r14}

	/* ?傝?傒?婣 */
        SUBS  pc, lr, #4
        
.globl	_abt
.globl	_fiq
.globl	_swi
.globl	_und

Noentry:
_abt:
_fiq:
_swi:
_und:
	b	Noentry
");

asm("
.globl	invalidate_d_cache

invalidate_d_cache:
bic		r2, r0, #31
add		r0, r0, r1
bic		r0, r0, #31

cmp		r2, r0
bxhi	lr
Loop_invalidate_d_cache:
mcr p15, 0, r2, c7, c6, 1

add		r2, r2, #32
cmp		r2, r0
bxhi	lr
b		Loop_invalidate_d_cache
");



main()
{
  // set DRAM arbitration priority to DPU
  pod(CCSP_ARBPRI_1_4,    	 0x0000f4f5); // cpu i=4,    cpu d=5
  pod(CCSP_ARBPRI_5_8,    	 0x0000f0f1); // DPU=0,      SPU=1
  pod(CCSP_ARBPRI_9_12,   	 0x00002f3f); // renderer=2, gle=3
  pod(CCSP_URG_ARBPRI_1_4,     0x0000f4f5); // cpu i=4,    cpu d=5
  pod(CCSP_URG_ARBPRI_5_8,     0x0000f0f1); // DPU=0,      SPU=1
  pod(CCSP_URG_ARBPRI_9_12,    0x00002f3f); // renderer=2, gle=3*/


  // initialize lcd
  //  init_block();
    color_bar();
   init_config();
 
   init_DPU(); 
    init_LCD();
    pod(VIDEO_SCR_ADDRESS_Y,0x00700000);
  
   while(1); 
  
  
 
}