/******************************************************************************* *              Copyright (c) 2000 LSI Logic Corporation - All Rights Reserved * * File:        $RCSfile: zsp_dmac.h,v $ * Revision:    $Revision: 1.1 $ * Date:        $Date: 2005/06/29 00:49:50 $ * Purpose:     Globals for ZSP DMA Controller * * ******************************************************************************/#ifndef _ZSP_DMAC_H#define _ZSP_DMAC_H/* DMA Controller registers */#define ZSP_MCDMAC_BASE      0xC0000000#define ZSP_MCDMAC_INT_REQ_REG      (ZSP_MCDMAC_BASE + (8*0))#define ZSP_MCDMAC_INT_SET_REG      (ZSP_MCDMAC_BASE + (8*1))#define ZSP_MCDMAC_INT_CLR_REG      (ZSP_MCDMAC_BASE + (8*2))#define ZSP_MCDMAC_INT_MSK_REG      (ZSP_MCDMAC_BASE + (8*3))#define ZSP_MCDMAC_EVN_REQ_REG      (ZSP_MCDMAC_BASE + (8*4))#define ZSP_MCDMAC_EVN_SET_REG      (ZSP_MCDMAC_BASE + (8*5))#define ZSP_MCDMAC_EVN_CLR_REG      (ZSP_MCDMAC_BASE + (8*6))#define ZSP_MCDMAC_CH_STAT_REG      (ZSP_MCDMAC_BASE + (8*7))#define ZSP_MCDMAC_ERR_INT_REQ_REG  (ZSP_MCDMAC_BASE + (8*8))#define ZSP_MCDMAC_ERR_INT_SET_REG  (ZSP_MCDMAC_BASE + (8*9))#define ZSP_MCDMAC_ERR_INT_CLR_REG  (ZSP_MCDMAC_BASE + (8*10))#define ZSP_MCDMAC_ERR_INT_MSK_REG  (ZSP_MCDMAC_BASE + (8*11))#define ZSP_MCDMAC_CH0_BASE         (ZSP_MCDMAC_BASE + (64*2))#define ZSP_MCDMAC_CH0_CNTL_REG     (ZSP_MCDMAC_CH0_BASE + (4*0))#define ZSP_MCDMAC_CH0_STAT_REG     (ZSP_MCDMAC_CH0_BASE + (4*1))#define ZSP_MCDMAC_CH0_NDLB_REG     (ZSP_MCDMAC_CH0_BASE + (4*2))#define ZSP_MCDMAC_CH0_CSRC_REG     (ZSP_MCDMAC_CH0_BASE + (4*3))#define ZSP_MCDMAC_CH0_CDES_REG     (ZSP_MCDMAC_CH0_BASE + (4*4))#define ZSP_MCDMAC_CH0_CDBA_REG     (ZSP_MCDMAC_CH0_BASE + (4*5))#define ZSP_MCDMAC_CH1_BASE         (ZSP_MCDMAC_BASE + (64*3))#define ZSP_MCDMAC_CH1_CNTL_REG     (ZSP_MCDMAC_CH1_BASE + (4*0))#define ZSP_MCDMAC_CH1_STAT_REG     (ZSP_MCDMAC_CH1_BASE + (4*1))#define ZSP_MCDMAC_CH1_NDLB_REG     (ZSP_MCDMAC_CH1_BASE + (4*2))#define ZSP_MCDMAC_CH1_CSRC_REG     (ZSP_MCDMAC_CH1_BASE + (4*3))#define ZSP_MCDMAC_CH1_CDES_REG     (ZSP_MCDMAC_CH1_BASE + (4*4))#define ZSP_MCDMAC_CH1_CDBA_REG     (ZSP_MCDMAC_CH1_BASE + (4*5))#define ZSP_MCDMAC_CCR_CMD_LSB      1#define ZSP_MCDMAC_CCR_CMD_MSB      3#define ZSP_MCDMAC_CCR_CMD_MSK      (((1<<(ZSP_MCDMAC_CCR_CMD_MSB-ZSP_MCDMAC_CCR_CMD_LSB+1))-1)<<ZSP_MCDMAC_CCR_CMD_MSB)#define CCR_NOCHANGE  0#define CCR_START     1#define CCR_PAUSE     2#define CCR_CONTINUE  3#define CCR_STOP_IMM  4#define CCR_STOP_AFT  5#define MCDMAC_CH0_CNTL_VALE    (CCR_START<<ZSP_MCDMAC_CCR_CMD_LSB)#define MCDMAC_CH1_CNTL_VALE    (CCR_START<<ZSP_MCDMAC_CCR_CMD_LSB)#define CCR_VALUE (CCR_START<<1)/*********************************************************************      ZSP MCDMA Transfer Configuration Field 1                  *********************************************************************/#define  FMT_MSB       1#define  FMT_LSB       0#define  FMT_MSK       (((1<<(FMT_MSB-FMT_LSB+1))-1)<<FMT_LSB)#define  SFA_MSB       5#define  SFA_LSB       2#define  SFA_MSK       (((1<<(SFA_MSB-SFA_LSB+1))-1)<<SFA_LSB)#define  DFA_MSB      11#define  DFA_LSB       8#define  DFA_MSK       (((1<<(DFA_MSB-DFA_LSB+1))-1)<<DFA_LSB)#define  DIM_MSB      15#define  DIM_LSB      14#define  DIM_MSK       (((1<<(DIM_MSB-DIM_LSB+1))-1)<<DIM_LSB)#define  IGEN_MSB     23#define  IGEN_LSB     21#define  IGEN_MSK      (((1<<(IGEN_MSB-IGEN_LSB+1))-1)<<IGEN_LSB)#define  ERM_MSB      27#define  ERM_LSB      24#define  ERM_MSK       (((1<<(ERM_MSB-ERM_LSB+1))-1)<<ERM_LSB)#define  ERI_MSB      31#define  ERI_LSB      28#define  ERI_MSK       (((1<<(ERI_MSB-ERI_LSB+1))-1)<<ERI_LSB)/*********************************************************************      ZSP MCDMA Transfer Configuration Field 2                  *********************************************************************/#define  EMOD_MSB      2#define  EMOD_LSB      0#define  EMOD_MSK      (((1<<(EMOD_MSB-EMOD_LSB+1))-1)<<EMOD_LSB)#define  EGEN_MSB     10#define  EGEN_LSB      4#define  EGEN_MSK      (((1<<(EGEN_MSB-EGEN_LSB+1))-1)<<EGEN_LSB)#define  SSIZ_MSB     13#define  SSIZ_LSB     11#define  SSIZ_MSK      (((1<<(SSIZ_MSB-SSIZ_LSB+1))-1)<<SSIZ_LSB)#define  DSIZ_MSB     16#define  DSIZ_LSB     14#define  DSIZ_MSK      (((1<<(DSIZ_MSB-DSIZ_LSB+1))-1)<<DSIZ_LSB)#define  PCK_MSB      22#define  PCK_LSB      19#define  PCK_MSK       (((1<<(PCK_MSB-PCK_LSB+1))-1)<<PCK_LSB)#define  BLIM_MSB     27#define  BLIM_LSB     24#define  BLIM_MSK      (((1<<(BLIM_MSB-BLIM_LSB+1))-1)<<BLIM_LSB)#define  BSTS_MSB     28#define  BSTS_LSB     28#define  BSTS_MSK      (((1<<(BSTS_MSB-BSTS_LSB+1))-1)<<BSTS_LSB)#define  BSTD_MSB     29#define  BSTD_LSB     29#define  BSTD_MSK      (((1<<(BSTD_MSB-BSTD_LSB+1))-1)<<BSTD_LSB)#endif /* _ZSP_DMAC_H */