?? armcore9_new.rpt
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Project Information f:\new_project\arm9_core\cpld\armcore9_new.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 02/29/2004 17:14:32
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
armcore9_new
EPM3032ATC44-10 17 12 0 12 0 37 %
User Pins: 17 12 0
Project Information f:\new_project\arm9_core\cpld\armcore9_new.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'test1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'test2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'nXDREQ0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'nWAIT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'CLKPUT0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'nXDACK0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'IDE_RDY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information f:\new_project\arm9_core\cpld\armcore9_new.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
armcore9_new@33 ADDR24
armcore9_new@34 BUF_DIR
armcore9_new@37 CLKPUT0
armcore9_new@22 EXT_CS
armcore9_new@21 EXT_OE
armcore9_new@20 EXT_WE
armcore9_new@13 IDE_OE
armcore9_new@18 IDE_RDY
armcore9_new@12 IDE_WE
armcore9_new@42 nEXTBUS
armcore9_new@43 nGCS0
armcore9_new@44 nGCS1
armcore9_new@2 nGCS2
armcore9_new@3 nGCS3
armcore9_new@5 nGCS4
armcore9_new@6 nGCS5
armcore9_new@25 nIOR_P
armcore9_new@27 nIOW_P
armcore9_new@28 nMEMR
armcore9_new@31 nMEMW
armcore9_new@35 nOE
armcore9_new@39 nRESET
armcore9_new@23 nUSB_EN
armcore9_new@19 nWAIT
armcore9_new@38 nWE
armcore9_new@10 nXDACK0
armcore9_new@8 nXDREQ0
armcore9_new@14 test1
armcore9_new@15 test2
Device-Specific Information: f:\new_project\arm9_core\cpld\armcore9_new.rpt
armcore9_new
***** Logic for device 'armcore9_new' compiled without errors.
Device: EPM3032ATC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: f:\new_project\arm9_core\cpld\armcore9_new.rpt
armcore9_new
** ERROR SUMMARY **
Info: Chip 'armcore9_new' in device 'EPM3032ATC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
n C B
E V n L U
n n X C R K F
G G T C E P _
C C B I G S n U G n D
S S U N N E W T N O I
1 0 S T D T E 0 D E R
-----------------------------------_
/ 44 43 42 41 40 39 38 37 36 35 34 |
#TDI | 1 33 | ADDR24
nGCS2 | 2 32 | #TDO
nGCS3 | 3 31 | nMEMW
GND | 4 30 | GND
nGCS4 | 5 29 | VCCIO
nGCS5 | 6 EPM3032ATC44-10 28 | nMEMR
#TMS | 7 27 | nIOW_P
nXDREQ0 | 8 26 | #TCK
VCCIO | 9 25 | nIOR_P
nXDACK0 | 10 24 | GND
GND | 11 23 | nUSB_EN
|_ 12 13 14 15 16 17 18 19 20 21 22 _|
------------------------------------
I I t t G V I n E E E
D D e e N C D W X X X
E E s s D C E A T T T
_ _ t t I _ I _ _ _
W O 1 2 N R T W O C
E E T D E E S
Y
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\new_project\arm9_core\cpld\armcore9_new.rpt
armcore9_new
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 15/15(100%) 0/16( 0%) 8/36( 22%)
B: LC17 - LC32 9/16( 56%) 15/15(100%) 0/16( 0%) 5/36( 13%)
Total dedicated input pins used: 3/4 ( 75%)
Total logic cells used: 12/32 ( 37%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 12/32 ( 37%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 1.91
Total fan-in: 23
Total input pins required: 17
Total output pins required: 12
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 12
Total flipflops required: 0
Total product terms required: 12
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: f:\new_project\arm9_core\cpld\armcore9_new.rpt
armcore9_new
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 (19) (B) INPUT 0 0 0 0 0 4 0 ADDR24
37 - - INPUT 0 0 0 0 0 0 0 CLKPUT0
18 (32) (B) INPUT 0 0 0 0 0 0 0 IDE_RDY
43 (2) (A) INPUT 0 0 0 0 0 1 0 nGCS0
44 (3) (A) INPUT 0 0 0 0 0 1 0 nGCS1
2 (5) (A) INPUT 0 0 0 0 0 1 0 nGCS2
3 (6) (A) INPUT 0 0 0 0 0 1 0 nGCS3
5 (7) (A) INPUT 0 0 0 0 0 3 0 nGCS4
6 (8) (A) INPUT 0 0 0 0 0 2 0 nGCS5
35 (17) (B) INPUT 0 0 0 0 0 5 0 nOE
39 - - INPUT 0 0 0 0 0 1 0 nRESET
19 (31) (B) INPUT 0 0 0 0 0 0 0 nWAIT
38 - - INPUT 0 0 0 0 0 4 0 nWE
10 (11) (A) INPUT 0 0 0 0 0 0 0 nXDACK0
8 (10) (A) INPUT 0 0 0 0 0 0 0 nXDREQ0
14 (15) (A) INPUT 0 0 0 0 0 0 0 test1
15 (16) (A) INPUT 0 0 0 0 0 0 0 test2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\new_project\arm9_core\cpld\armcore9_new.rpt
armcore9_new
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
34 18 B OUTPUT t 0 0 0 1 0 0 0 BUF_DIR
22 28 B OUTPUT t 0 0 0 1 0 0 0 EXT_CS
21 29 B OUTPUT t 0 0 0 1 0 0 0 EXT_OE
20 30 B OUTPUT t 0 0 0 1 0 0 0 EXT_WE
13 14 A OUTPUT t 0 0 0 2 0 0 0 IDE_OE
12 13 A OUTPUT t 0 0 0 2 0 0 0 IDE_WE
42 1 A OUTPUT t 0 0 0 6 0 0 0 nEXTBUS
25 26 B OUTPUT t 0 0 0 2 0 0 0 nIOR_P
27 24 B OUTPUT t 0 0 0 2 0 0 0 nIOW_P
28 23 B OUTPUT t 0 0 0 2 0 0 0 nMEMR
31 21 B OUTPUT t 0 0 0 2 0 0 0 nMEMW
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