;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 240   ;
;     -- arithmetic mode                      ; 35    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 2     ;
;     -- asynchronous clear/load mode         ; 79    ;
;                                             ;       ;
; Total registers                             ; 79    ;
; Total logic cells in carry chains           ; 38    ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 79    ;
; Total fan-out                               ; 1055  ;
; Average fan-out                             ; 3.56  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |i2c                       ; 275 (275)   ; 79           ; 0          ; 21   ; 0            ; 196 (196)    ; 26 (26)           ; 53 (53)          ; 38 (38)         ; 0 (0)      ; |i2c                ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+---------------------------------------------------------------+
; State Machine - |i2c|main_state                               ;
+---------------+---------------+---------------+---------------+
; Name          ; main_state.00 ; main_state.10 ; main_state.01 ;
+---------------+---------------+---------------+---------------+
; main_state.00 ; 0             ; 0             ; 0             ;
; main_state.01 ; 1             ; 0             ; 1             ;
; main_state.10 ; 1             ; 1             ; 0             ;
+---------------+---------------+---------------+---------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------+
; State Machine - |i2c|i2c_state                                                                                              ;
+----------------------+---------------------+--------------------+----------------------+---------------+--------------------+
; Name                 ; i2c_state.read_data ; i2c_state.sendaddr ; i2c_state.write_data ; i2c_state.ini ; i2c_state.read_ini ;
+----------------------+---------------------+--------------------+----------------------+---------------+--------------------+
; i2c_state.ini        ; 0                   ; 0                  ; 0                    ; 0             ; 0                  ;
; i2c_state.read_ini   ; 0                   ; 0                  ; 0                    ; 1             ; 1                  ;
; i2c_state.write_data ; 0                   ; 0                  ; 1                    ; 1             ; 0                  ;
; i2c_state.sendaddr   ; 0                   ; 1                  ; 0                    ; 1             ; 0                  ;
; i2c_state.read_data  ; 1                   ; 0                  ; 0                    ; 1             ; 0                  ;
+----------------------+---------------------+--------------------+----------------------+---------------+--------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |i2c|inner_state                                                                                                                                                                                                                  ;
+---------------------+------------------+-------------------+--------------------+-------------------+--------------------+-------------------+-------------------+---------------------+--------------------+-----------------+-------------------+
; Name                ; inner_state.stop ; inner_state.first ; inner_state.second ; inner_state.third ; inner_state.fourth ; inner_state.fifth ; inner_state.sixth ; inner_state.seventh ; inner_state.eighth ; inner_state.ack ; inner_state.start ;
+---------------------+------------------+-------------------+--------------------+-------------------+--------------------+-------------------+-------------------+---------------------+--------------------+-----------------+-------------------+
; inner_state.start   ; 0                ; 0                 ; 0                  ; 0                 ; 0                  ; 0                 ; 0                 ; 0                   ; 0                  ; 0               ; 0                 ;
; inner_state.ack     ; 0                ; 0                 ; 0                  ; 0                 ; 0                  ; 0                 ; 0                 ; 0                   ; 0                  ; 1               ; 1                 ;
; inner_state.eighth  ; 0                ; 0                 ; 0                  ; 0                 ; 0                  ; 0                 ; 0                 ; 0                   ; 1                  ; 0               ; 1                 ;
; inner_state.seventh ; 0                ; 0                 ; 0                  ; 0                 ; 0                  ; 0                 ; 0                 ; 1                   ; 0                  ; 0               ; 1                 ;
; inner_state.sixth   ; 0                ; 0                 ; 0                  ; 0                 ; 0                  ; 0                 ; 1                 ; 0                   ; 0                  ; 0               ; 1                 ;
; inner_state.fifth   ; 0                ; 0                 ; 0                  ; 0                 ; 0                  ; 1                 ; 0                 ; 0                   ; 0                  ; 0               ; 1                 ;
; inner_state.fourth  ; 0                ; 0                 ; 0                  ; 0                 ; 1                  ; 0                 ; 0                 ; 0                   ; 0                  ; 0               ; 1                 ;
; inner_state.third   ; 0                ; 0                 ; 0                  ; 1                 ; 0                  ; 0                 ; 0                 ; 0                   ; 0                  ; 0               ; 1                 ;
; inner_state.second  ; 0                ; 0                 ; 1                  ; 0                 ; 0                  ; 0                 ; 0                 ; 0                   ; 0                  ; 0               ; 1                 ;
; inner_state.first   ; 0                ; 1                 ; 0                  ; 0                 ; 0                  ; 0                 ; 0                 ; 0                   ; 0                  ; 0               ; 1                 ;
; inner_state.stop    ; 1                ; 0                 ; 0                  ; 0                 ; 0                  ; 0                 ; 0                 ; 0                   ; 0                  ; 0               ; 1                 ;
+---------------------+------------------+-------------------+--------------------+-------------------+--------------------+-------------------+-------------------+---------------------+--------------------+-----------------+-------------------+


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; writeData_reg[7]                       ; Stuck at GND due to stuck port data_in ;
; writeData_reg[6]                       ; Stuck at GND due to stuck port data_in ;
; writeData_reg[5]                       ; Stuck at GND due to stuck port data_in ;
; writeData_reg[4]                       ; Stuck at GND due to stuck port data_in ;
; i2c_state~65                           ; Lost fanout                            ;
; i2c_state~66                           ; Lost fanout                            ;
; inner_state~140                        ; Lost fanout                            ;
; inner_state~141                        ; Lost fanout                            ;
; inner_state~142                        ; Lost fanout                            ;
; inner_state~143                        ; Lost fanout                            ;
; clk_div[0]                             ; Merged with cnt_scan[0]                ;
; clk_div[1]                             ; Merged with cnt_scan[1]                ;
; Total Number of Removed Registers = 12 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 79    ;
; Number of registers using Synchronous Clear  ; 2     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 79    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 35    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; scl~reg0                               ; 2       ;
; en[1]~reg0                             ; 8       ;
; writeData_reg[0]                       ; 2       ;
; writeData_reg[2]                       ; 2       ;
; sda_buf                                ; 20      ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |i2c|readData_reg[5]       ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; No         ; |i2c|i2c_state~5           ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; No         ; |i2c|Selector92            ;
; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |i2c|Selector13            ;
; 14:1               ; 2 bits    ; 18 LEs        ; 6 LEs                ; 12 LEs                 ; No         ; |i2c|Selector45            ;
; 15:1               ; 3 bits    ; 30 LEs        ; 9 LEs                ; 21 LEs                 ; No         ; |i2c|Selector130           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+