Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Jul 06 20:50:49 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off i2c -c i2c
Info: Selected device EPM1270T144C5 for design "i2c"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock
Info: Pin "clk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "data_in[4]" is assigned to location or region, but does not exist in design
    Warning: Node "data_in[5]" is assigned to location or region, but does not exist in design
    Warning: Node "data_in[6]" is assigned to location or region, but does not exist in design
    Warning: Node "data_in[7]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 10.297 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y7; Fanout = 18; REG Node = 'inner_state.stop'
    Info: 2: + IC(1.159 ns) + CELL(0.200 ns) = 1.359 ns; Loc. = LAB_X10_Y7; Fanout = 5; COMB Node = 'readData_reg[0]~85'
    Info: 3: + IC(1.382 ns) + CELL(0.200 ns) = 2.941 ns; Loc. = LAB_X11_Y7; Fanout = 1; COMB Node = 'Selector66~408'
    Info: 4: + IC(0.983 ns) + CELL(0.200 ns) = 4.124 ns; Loc. = LAB_X11_Y7; Fanout = 1; COMB Node = 'Selector66~409'
    Info: 5: + IC(1.615 ns) + CELL(0.740 ns) = 6.479 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Selector111~901'
    Info: 6: + IC(0.269 ns) + CELL(0.914 ns) = 7.662 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Selector111~903'
    Info: 7: + IC(0.443 ns) + CELL(0.740 ns) = 8.845 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Selector111~904'
    Info: 8: + IC(0.269 ns) + CELL(1.183 ns) = 10.297 ns; Loc. = LAB_X11_Y5; Fanout = 11; REG Node = 'link'
    Info: Total cell delay = 4.177 ns ( 40.57 % )
    Info: Total interconnect delay = 6.120 ns ( 59.43 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 9%
    Info: The peak interconnect region extends from location X9_Y0 to location X17_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:01
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin lowbit has GND driving its datain port
    Info: Pin seg_data[0] has VCC driving its datain port
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: link
        Info: Type bidirectional pin sda uses the 3.3-V LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 6 warnings
    Info: Allocated 158 megabytes of memory during processing
    Info: Processing ended: Sun Jul 06 20:50:54 2008
    Info: Elapsed time: 00:00:05