?? i2c.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic
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-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
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-- applicable agreement for further details.
--A1L613Q is scl~reg0
--operation mode is normal
A1L613Q_lut_out = !phase0 & main_state.00 & (A1L613Q # phase2);
A1L613Q = DFFEAS(A1L613Q_lut_out, clk, rst, , , , , , );
--A1L242Q is en[0]~reg0
--operation mode is normal
A1L242Q_lut_out = !A1L242Q;
A1L242Q = DFFEAS(A1L242Q_lut_out, clk, rst, , A1L192, , , , );
--A1L442Q is en[1]~reg0
--operation mode is normal
A1L442Q_lut_out = !A1L442Q;
A1L442Q = DFFEAS(A1L442Q_lut_out, clk, rst, , A1L192, , , , );
--readData_reg[3] is readData_reg[3]
--operation mode is normal
readData_reg[3]_lut_out = readData_reg[2];
readData_reg[3] = DFFEAS(readData_reg[3]_lut_out, clk, rst, , A1L582, , , , );
--writeData_reg[3] is writeData_reg[3]
--operation mode is normal
writeData_reg[3]_lut_out = data_in[3];
writeData_reg[3] = DFFEAS(writeData_reg[3]_lut_out, clk, rst, , !main_state.00, , , , );
--A1L433 is seg_data_buf[3]~534
--operation mode is normal
A1L433 = A1L242Q & readData_reg[3] & A1L442Q # !A1L242Q & (!A1L442Q & writeData_reg[3]);
--readData_reg[2] is readData_reg[2]
--operation mode is normal
readData_reg[2]_lut_out = readData_reg[1];
readData_reg[2] = DFFEAS(readData_reg[2]_lut_out, clk, rst, , A1L582, , , , );
--writeData_reg[2] is writeData_reg[2]
--operation mode is normal
writeData_reg[2]_lut_out = !data_in[2];
writeData_reg[2] = DFFEAS(writeData_reg[2]_lut_out, clk, rst, , !main_state.00, , , , );
--A1L333 is seg_data_buf[2]~535
--operation mode is normal
A1L333 = A1L242Q & readData_reg[2] & A1L442Q # !A1L242Q & (!A1L442Q & !writeData_reg[2]);
--readData_reg[1] is readData_reg[1]
--operation mode is normal
readData_reg[1]_lut_out = readData_reg[0];
readData_reg[1] = DFFEAS(readData_reg[1]_lut_out, clk, rst, , A1L582, , , , );
--writeData_reg[1] is writeData_reg[1]
--operation mode is normal
writeData_reg[1]_lut_out = data_in[1];
writeData_reg[1] = DFFEAS(writeData_reg[1]_lut_out, clk, rst, , !main_state.00, , , , );
--A1L233 is seg_data_buf[1]~536
--operation mode is normal
A1L233 = A1L242Q & readData_reg[1] & A1L442Q # !A1L242Q & (!A1L442Q & writeData_reg[1]);
--readData_reg[0] is readData_reg[0]
--operation mode is normal
readData_reg[0]_lut_out = A1L123;
readData_reg[0] = DFFEAS(readData_reg[0]_lut_out, clk, rst, , A1L582, , , , );
--writeData_reg[0] is writeData_reg[0]
--operation mode is normal
writeData_reg[0]_lut_out = !data_in[0];
writeData_reg[0] = DFFEAS(writeData_reg[0]_lut_out, clk, rst, , !main_state.00, , , , );
--A1L133 is seg_data_buf[0]~537
--operation mode is normal
A1L133 = A1L242Q & readData_reg[0] & A1L442Q # !A1L242Q & (!A1L442Q & !writeData_reg[0]);
--A1L892 is reduce_or~2138
--operation mode is normal
A1L892 = A1L133 & (A1L433 # A1L333 $ A1L233) # !A1L133 & (A1L233 # A1L433 $ A1L333);
--readData_reg[7] is readData_reg[7]
--operation mode is normal
readData_reg[7]_lut_out = readData_reg[6];
readData_reg[7] = DFFEAS(readData_reg[7]_lut_out, clk, rst, , A1L582, , , , );
--readData_reg[5] is readData_reg[5]
--operation mode is normal
readData_reg[5]_lut_out = readData_reg[4];
readData_reg[5] = DFFEAS(readData_reg[5]_lut_out, clk, rst, , A1L582, , , , );
--A1L992 is reduce_or~2139
--operation mode is normal
A1L992 = !readData_reg[7] & !readData_reg[5] # !A1L442Q # !A1L242Q;
--readData_reg[6] is readData_reg[6]
--operation mode is normal
readData_reg[6]_lut_out = readData_reg[5];
readData_reg[6] = DFFEAS(readData_reg[6]_lut_out, clk, rst, , A1L582, , , , );
--readData_reg[4] is readData_reg[4]
--operation mode is normal
readData_reg[4]_lut_out = readData_reg[3];
readData_reg[4] = DFFEAS(readData_reg[4]_lut_out, clk, rst, , A1L582, , , , );
--A1L003 is reduce_or~2140
--operation mode is normal
A1L003 = !readData_reg[6] & !readData_reg[4] # !A1L442Q # !A1L242Q;
--A1L103 is reduce_or~2141
--operation mode is normal
A1L103 = !A1L003 # !A1L992 # !A1L892;
--A1L203 is reduce_or~2142
--operation mode is normal
A1L203 = A1L333 & A1L133 & (A1L433 $ A1L233) # !A1L333 & !A1L433 & (A1L233 # A1L133);
--A1L303 is reduce_or~2143
--operation mode is normal
A1L303 = A1L203 # !A1L003 # !A1L992;
--A1L403 is reduce_or~2144
--operation mode is normal
A1L403 = A1L233 & !A1L433 & (A1L133) # !A1L233 & (A1L333 & !A1L433 # !A1L333 & (A1L133));
--A1L503 is reduce_or~2145
--operation mode is normal
A1L503 = A1L403 # !A1L003 # !A1L992;
--A1L603 is reduce_or~2146
--operation mode is normal
A1L603 = A1L133 & (A1L333 $ !A1L233) # !A1L133 & (A1L433 & !A1L333 & A1L233 # !A1L433 & A1L333 & !A1L233);
--A1L703 is reduce_or~2147
--operation mode is normal
A1L703 = A1L603 # !A1L003 # !A1L992;
--A1L803 is reduce_or~2148
--operation mode is normal
A1L803 = A1L433 & A1L333 & (A1L233 # !A1L133) # !A1L433 & !A1L333 & A1L233 & !A1L133;
--A1L903 is reduce_or~2149
--operation mode is normal
A1L903 = A1L803 # !A1L003 # !A1L992;
--A1L013 is reduce_or~2150
--operation mode is normal
A1L013 = A1L433 & (A1L133 & (A1L233) # !A1L133 & A1L333) # !A1L433 & A1L333 & (A1L233 $ A1L133);
--A1L113 is reduce_or~2151
--operation mode is normal
A1L113 = A1L013 # !A1L003 # !A1L992;
--A1L213 is reduce_or~2152
--operation mode is normal
A1L213 = A1L433 & A1L133 & (A1L333 $ A1L233) # !A1L433 & !A1L233 & (A1L333 $ A1L133);
--A1L313 is reduce_or~2153
--operation mode is normal
A1L313 = A1L213 # !A1L003 # !A1L992;
--phase0 is phase0
--operation mode is normal
phase0_lut_out = !phase0 & !clk_div[3] & A1L292 & A1L392;
phase0 = DFFEAS(phase0_lut_out, clk, rst, , , , , , );
--phase2 is phase2
--operation mode is normal
phase2_lut_out = !phase2 & !clk_div[3] & A1L292 & A1L172;
phase2 = DFFEAS(phase2_lut_out, clk, rst, , , , , , );
--main_state.00 is main_state.00
--operation mode is normal
main_state.00_lut_out = !A1L2 & !A1L011 & (!A1L8 # !A1L6);
main_state.00 = DFFEAS(main_state.00_lut_out, clk, rst, , , , , , );
--cnt_scan[1] is cnt_scan[1]
--operation mode is arithmetic
cnt_scan[1]_lut_out = cnt_scan[1] $ clk_div[0];
cnt_scan[1] = DFFEAS(cnt_scan[1]_lut_out, clk, rst, , , , , , );
--A1L512 is cnt_scan[1]~184
--operation mode is arithmetic
A1L512 = CARRY(cnt_scan[1] & clk_div[0]);
--cnt_scan[2] is cnt_scan[2]
--operation mode is arithmetic
cnt_scan[2]_carry_eqn = A1L512;
cnt_scan[2]_lut_out = cnt_scan[2] $ (cnt_scan[2]_carry_eqn);
cnt_scan[2] = DFFEAS(cnt_scan[2]_lut_out, clk, rst, , , , , , );
--A1L712 is cnt_scan[2]~188
--operation mode is arithmetic
A1L712 = CARRY(!A1L512 # !cnt_scan[2]);
--cnt_scan[3] is cnt_scan[3]
--operation mode is arithmetic
cnt_scan[3]_carry_eqn = A1L712;
cnt_scan[3]_lut_out = cnt_scan[3] $ (!cnt_scan[3]_carry_eqn);
cnt_scan[3] = DFFEAS(cnt_scan[3]_lut_out, clk, rst, , , , , , );
--A1L912 is cnt_scan[3]~192
--operation mode is arithmetic
A1L912 = CARRY(cnt_scan[3] & (!A1L712));
--clk_div[0] is clk_div[0]
--operation mode is normal
clk_div[0]_lut_out = A1L121;
clk_div[0] = DFFEAS(clk_div[0]_lut_out, clk, rst, , , , , , );
--A1L882 is reduce_nor~273
--operation mode is normal
A1L882 = !clk_div[0] # !cnt_scan[3] # !cnt_scan[2] # !cnt_scan[1];
--cnt_scan[4] is cnt_scan[4]
--operation mode is arithmetic
cnt_scan[4]_carry_eqn = A1L912;
cnt_scan[4]_lut_out = cnt_scan[4] $ (cnt_scan[4]_carry_eqn);
cnt_scan[4] = DFFEAS(cnt_scan[4]_lut_out, clk, rst, , , , , , );
--A1L122 is cnt_scan[4]~196
--operation mode is arithmetic
A1L122 = CARRY(!A1L912 # !cnt_scan[4]);
--cnt_scan[5] is cnt_scan[5]
--operation mode is arithmetic
cnt_scan[5]_carry_eqn = A1L122;
cnt_scan[5]_lut_out = cnt_scan[5] $ (!cnt_scan[5]_carry_eqn);
cnt_scan[5] = DFFEAS(cnt_scan[5]_lut_out, clk, rst, , , , , , );
--A1L322 is cnt_scan[5]~200
--operation mode is arithmetic
A1L322 = CARRY(cnt_scan[5] & (!A1L122));
--cnt_scan[6] is cnt_scan[6]
--operation mode is arithmetic
cnt_scan[6]_carry_eqn = A1L322;
cnt_scan[6]_lut_out = cnt_scan[6] $ (cnt_scan[6]_carry_eqn);
cnt_scan[6] = DFFEAS(cnt_scan[6]_lut_out, clk, rst, , , , , , );
--A1L522 is cnt_scan[6]~204
--operation mode is arithmetic
A1L522 = CARRY(!A1L322 # !cnt_scan[6]);
--cnt_scan[7] is cnt_scan[7]
--operation mode is arithmetic
cnt_scan[7]_carry_eqn = A1L522;
cnt_scan[7]_lut_out = cnt_scan[7] $ (!cnt_scan[7]_carry_eqn);
cnt_scan[7] = DFFEAS(cnt_scan[7]_lut_out, clk, rst, , , , , , );
--A1L722 is cnt_scan[7]~208
--operation mode is arithmetic
A1L722 = CARRY(cnt_scan[7] & (!A1L522));
--A1L982 is reduce_nor~274
--operation mode is normal
A1L982 = !cnt_scan[7] # !cnt_scan[6] # !cnt_scan[5] # !cnt_scan[4];
--cnt_scan[8] is cnt_scan[8]
--operation mode is arithmetic
cnt_scan[8]_carry_eqn = A1L722;
cnt_scan[8]_lut_out = cnt_scan[8] $ (cnt_scan[8]_carry_eqn);
cnt_scan[8] = DFFEAS(cnt_scan[8]_lut_out, clk, rst, , , , , , );
--A1L922 is cnt_scan[8]~212
--operation mode is arithmetic
A1L922 = CARRY(!A1L722 # !cnt_scan[8]);
--cnt_scan[9] is cnt_scan[9]
--operation mode is arithmetic
cnt_scan[9]_carry_eqn = A1L922;
cnt_scan[9]_lut_out = cnt_scan[9] $ (!cnt_scan[9]_carry_eqn);
cnt_scan[9] = DFFEAS(cnt_scan[9]_lut_out, clk, rst, , , , , , );
--A1L132 is cnt_scan[9]~216
--operation mode is arithmetic
A1L132 = CARRY(cnt_scan[9] & (!A1L922));
--cnt_scan[10] is cnt_scan[10]
--operation mode is arithmetic
cnt_scan[10]_carry_eqn = A1L132;
cnt_scan[10]_lut_out = cnt_scan[10] $ (cnt_scan[10]_carry_eqn);
cnt_scan[10] = DFFEAS(cnt_scan[10]_lut_out, clk, rst, , , , , , );
--A1L332 is cnt_scan[10]~220
--operation mode is arithmetic
A1L332 = CARRY(!A1L132 # !cnt_scan[10]);
--cnt_scan[11] is cnt_scan[11]
--operation mode is normal
cnt_scan[11]_carry_eqn = A1L332;
cnt_scan[11]_lut_out = cnt_scan[11] $ (!cnt_scan[11]_carry_eqn);
cnt_scan[11] = DFFEAS(cnt_scan[11]_lut_out, clk, rst, , , , , , );
--A1L092 is reduce_nor~275
--operation mode is normal
A1L092 = !cnt_scan[11] # !cnt_scan[10] # !cnt_scan[9] # !cnt_scan[8];
--A1L192 is reduce_nor~276
--operation mode is normal
A1L192 = !A1L882 & !A1L982 & !A1L092;
--phase1 is phase1
--operation mode is normal
phase1_lut_out = phase1 # !A1L682;
phase1 = DFFEAS(phase1_lut_out, clk, rst, , , , , phase1, );
--main_state.10 is main_state.10
--operation mode is normal
main_state.10_lut_out = !A1L011 & (A1L11 & wr_input # !A1L11 & (A1L111));
main_state.10 = DFFEAS(main_state.10_lut_out, clk, rst, , , , , , );
--i2c_state.read_data is i2c_state.read_data
--operation mode is normal
i2c_state.read_data_lut_out = i2c_state.read_data & (A1L31 # A1L052 & A1L21) # !i2c_state.read_data & A1L052 & A1L21;
i2c_state.read_data = DFFEAS(i2c_state.read_data_lut_out, clk, rst, , , , , , );
--A1L382 is readData_reg[7]~74
--operation mode is normal
A1L382 = main_state.10 & i2c_state.read_data;
--inner_state.start is inner_state.start
--operation mode is normal
inner_state.start_lut_out = !A1L71 & !A1L81 & main_state.10 # !A1L41;
inner_state.start = DFFEAS(inner_state.start_lut_out, clk, rst, , , , , , );
--inner_state.stop is inner_state.stop
--operation mode is normal
inner_state.stop_lut_out = inner_state.stop & (A1L31 # A1L052 & A1L91) # !inner_state.stop & A1L052 & A1L91;
inner_state.stop = DFFEAS(inner_state.stop_lut_out, clk, rst, , , , , , );
--A1L482 is readData_reg[7]~75
--operation mode is normal
A1L482 = inner_state.start & (!inner_state.stop);
--inner_state.ack is inner_state.ack
--operation mode is normal
inner_state.ack_lut_out = A1L22 # A1L42 # A1L92 & A1L03;
inner_state.ack = DFFEAS(inner_state.ack_lut_out, clk, rst, , , , , , );
--A1L582 is readData_reg[7]~76
--operation mode is normal
A1L582 = phase1 & A1L382 & A1L482 & !inner_state.ack;
--clk_div[3] is clk_div[3]
--operation mode is normal
clk_div[3]_lut_out = A1L321;
clk_div[3] = DFFEAS(clk_div[3]_lut_out, clk, rst, , , , , , );
--clk_div[5] is clk_div[5]
--operation mode is normal
clk_div[5]_lut_out = A1L521 & (clk_div[3] # !A1L392 # !A1L292);
clk_div[5] = DFFEAS(clk_div[5]_lut_out, clk, rst, , , , , , );
--clk_div[7] is clk_div[7]
--operation mode is normal
clk_div[7]_lut_out = A1L721;
clk_div[7] = DFFEAS(clk_div[7]_lut_out, clk, rst, , , , , , );
--clk_div[2] is clk_div[2]
--operation mode is normal
clk_div[2]_lut_out = A1L821 & (clk_div[3] # !A1L392 # !A1L292);
clk_div[2] = DFFEAS(clk_div[2]_lut_out, clk, rst, , , , , , );
--A1L292 is reduce_nor~277
--operation mode is normal
A1L292 = clk_div[0] & clk_div[5] & !clk_div[7] & !clk_div[2];
--clk_div[6] is clk_div[6]
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