VERSION=1.21
HEADER
FILE="SIETransmitter.asf"
FID=4094ffa4
LANGUAGE=VERILOG
ENTITY="SIETransmitter"
FREEOID=1083
"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
MULTIPLEARCHSTATUS=FALSE
SYNTHESISATTRIBUTES=TRUE
HEADER_PARAM="AUTHOR,"
HEADER_PARAM="COMPANY,"
HEADER_PARAM="CREATIONDATE,"
HEADER_PARAM="TITLE,No Title"
BLOCKTABLE_FILE=""
BLOCKTABLE_TEMPL="0"
BLOCKTABLE_VISIBLE="1"
END
BUNDLES
B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0
B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
END
INSTHEADER 1
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INSTHEADER 16
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INSTHEADER 213
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INSTHEADER 359
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INSTHEADER 455
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INSTHEADER 465
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INSTHEADER 474
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INSTHEADER 483
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INSTHEADER 609
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INSTHEADER 617
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INSTHEADER 626
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INSTHEADER 720
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INSTHEADER 717
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INSTHEADER 911
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INSTHEADER 958
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INSTHEADER 1073
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END
OBJECTS
L 831 832 0 TEXT "Labels" | 21372,210032 1 0 0 "USBWireWEn"
I 830 0 2 Builtin OutPort | 15372,214672 "" ""
L 829 830 0 TEXT "Labels" | 21372,214672 1 0 0 "USBWireReq"
I 828 0 2 Builtin InPort | 17692,219080 "" ""
L 827 828 0 TEXT "Labels" | 23692,219080 1 0 0 "USBWireGnt"
I 826 0 2 Builtin OutPort | 15372,223488 "" ""
L 825 826 0 TEXT "Labels" | 21140,223024 1 0 0 "USBWireCtrl"
I 824 0 130 Builtin OutPort | 15604,227896 "" ""
L 823 824 0 TEXT "Labels" | 21604,227896 1 0 0 "USBWireData[1:0]"
I 822 0 130 Builtin OutPort | 64372,233958 "" ""
L 821 822 0 TEXT "Labels" | 70372,233958 1 0 0 "TxByteOutCtrl[7:0]"
I 820 0 130 Builtin OutPort | 64372,238598 "" ""
L 819 820 0 TEXT "Labels" | 70372,238598 1 0 0 "TxByteOut[7:0]"
I 818 0 2 Builtin InPort | 66692,243238 "" ""
L 817 818 0 TEXT "Labels" | 72692,243238 1 0 0 "processTxByteRdy"
I 816 0 2 Builtin OutPort | 64372,247878 "" ""
L 15 16 0 TEXT "State Labels" | 115356,112006 1 0 0 "RES_ST"
W 13 6 0 12 9 BEZIER "Transitions" | 22016,192062 26512,191798 31110,187768 35074,185908
I 12 6 0 Builtin Reset | 22016,192062
S 11 6 0 ELLIPSE "States" | 41526,162904 6500 6500
L 10 11 0 TEXT "State Labels" | 41526,162904 1 0 0 "STX_CHK_ST\n/19/"
G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,253485 1 0 0 "Module: SIETransmitter"
F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,3000 199488,196819
L 7 6 0 TEXT "Labels" | 57079,194838 1 0 0 "SIETx"
L 8 9 0 TEXT "State Labels" | 41526,185122 1 0 0 "START_SIETX\n/18/"
S 9 6 0 ELLIPSE "States" | 41526,185122 6500 6500
I 847 0 130 Builtin InPort | 124599,206947 "" ""
I 846 0 130 Builtin InPort | 125108,202306 "" ""
L 845 846 0 TEXT "Labels" | 131108,202306 1 0 0 "KBit[1:0]"
I 844 0 130 Builtin Signal | 71500,203136 "" ""
L 843 844 0 TEXT "Labels" | 74500,203136 1 0 0 "i[2:0]"
I 840 0 130 Builtin Signal | 71500,207544 "" ""
L 839 840 0 TEXT "Labels" | 74500,207544 1 0 0 "SIEPortCtrl[7:0]"
I 838 0 130 Builtin Signal | 71732,211952 "" ""
L 837 838 0 TEXT "Labels" | 74732,211952 1 0 0 "SIEPortData[7:0]"
A 836 63 4 TEXT "Actions" | 118825,182282 1 0 0 "SIEPortTxRdy <= 1'b1;"
I 834 0 2 Builtin InPort | 17692,205624 "" ""
L 833 834 0 TEXT "Labels" | 23692,205624 1 0 0 "USBWireRdy"
I 832 0 2 Builtin OutPort | 15372,210032 "" ""
H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,110404 6500 6500
S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/31/"
W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/10/"
A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
I 572 458 0 Builtin Entry | 44780,253519
A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
A 835 9 4 TEXT "Actions" | 153876,195027 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
L 848 847 0 TEXT "Labels" | 130599,206947 1 0 0 "JBit[1:0]"
L 319 320 0 TEXT "Labels" | 133337,213507 1 0 0 "fullSpeedRateIn"
I 318 0 2 Builtin OutPort | 123866,228310 "" ""
L 317 318 0 TEXT "Labels" | 129866,228310 1 0 0 "CRC5_8Bit"
I 316 0 2 Builtin OutPort | 123509,232929 "" ""
L 315 316 0 TEXT "Labels" | 129509,232929 1 0 0 "CRC5En"
I 314 0 130 Builtin InPort | 125655,237903 "" ""
L 313 314 0 TEXT "Labels" | 131655,237903 1 0 0 "CRC5Result[4:0]"
I 312 0 130 Builtin OutPort | 123156,242520 "" ""
L 311 312 0 TEXT "Labels" | 129156,242520 1 0 0 "CRCData[7:0]"
I 310 0 2 Builtin OutPort | 123515,247488 "" ""
L 309 310 0 TEXT "Labels" | 129515,247488 1 0 0 "rstCRC"
I 606 489 0 Builtin Exit | 101068,51939
I 599 489 0 Builtin Entry | 29952,254306
I 324 0 130 Builtin InPort | 126267,223282 "" ""
L 323 324 0 TEXT "Labels" | 132267,223282 1 0 0 "CRC16Result[15:0]"
I 320 0 2 Builtin InPort | 127337,213507 "" ""
S 63 6 0 ELLIPSE "States" | 138700,164805 6500 6500
L 62 63 0 TEXT "State Labels" | 139687,163978 1 0 0 "STX_WAIT_BYTE\n/20/"
C 55 51 0 TEXT "Conditions" | 43286,108515 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
W 51 6 0 11 16 BEZIER "Transitions" | 41219,156419 41353,150657 41254,124742 41790,120856\
                                      42326,116970 44202,112950 52711,111811 61220,110672\
                                      92777,110593 108857,110325
I 872 360 0 Builtin Exit | 188676,86316
S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
W 351 6 0 911 63 BEZIER "Transitions" | 165111,75772 164661,79912 166410,89760 164070,92955\
                                        161730,96150 152965,99917 149770,102482 146575,105047\
                                        142560,111540 140625,118020 138690,124500 144540,143115\
                                        141750,148605 138960,154095 141442,152739 137520,158418
A 78 65 16 TEXT "Actions" | 53177,174464 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
W 68 6 0 16 911 BEZIER "Transitions" | 120272,106153 129598,96743 150861,80396 161245,74146
C 66 65 0 TEXT "Conditions" | 70342,152867 1 0 0 "SIEPortWEn == 1'b1"
W 65 6 0 63 11 BEZIER "Transitions" | 132240,164092 119927,158464 59299,161871 47927,164030
S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
S 911 6 4116 ELLIPSE "Junction" | 164265,72378 3500 3500
L 910 911 0 TEXT "State Labels" | 164265,72378 1 0 0 "J1"
C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
I 636 610 0 Builtin Entry | 71380,236621
S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500