?? mcu_ctrl.rpt
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Project Information d:\fast_adc\mcu_ctrl.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/27/2007 08:26:40
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mcu_ctrl EPM7064SLC44-10 10 16 0 21 0 32 %
User Pins: 10 16 0
Project Information d:\fast_adc\mcu_ctrl.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'P07' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'P06' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'P05' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Warning: Node 'Lcd1En' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Warning: Node 'Lcd2En' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Warning: Node 'RD' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Warning: Node 'WR' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Project Information d:\fast_adc\mcu_ctrl.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
mcu_ctrl@43 ALE
mcu_ctrl@41 --------- Lcd1En
mcu_ctrl@16 --------- Lcd2En
mcu_ctrl@17 P00
mcu_ctrl@18 P01
mcu_ctrl@19 P02
mcu_ctrl@20 P03
mcu_ctrl@21 P04
mcu_ctrl@24 P05
mcu_ctrl@25 P06
mcu_ctrl@26 P07
mcu_ctrl@1 P27
mcu_ctrl@44 --------- RD
mcu_ctrl@2 --------- WR
Project Information d:\fast_adc\mcu_ctrl.rpt
** FILE HIERARCHY **
|74373:112|
|74154:116|
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
***** Logic for device 'mcu_ctrl' compiled without errors.
Device: EPM7064SLC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R R R
E E E
S S S
E E E
R R R
V V V V G P G A G
E E E C N 2 N L N Y Y
D D D C D 7 D E D 1 0
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | Y4
RESERVED | 8 38 | #TDO
Y15 | 9 37 | Y5
GND | 10 36 | Y3
Y13 | 11 35 | VCC
Y14 | 12 EPM7064SLC44-10 34 | Y2
#TMS | 13 33 | Y6
Y11 | 14 32 | #TCK
VCC | 15 31 | Y7
Y12 | 16 30 | GND
P00 | 17 29 | Y8
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
P P P P G V P P P Y Y
0 0 0 0 N C 0 0 0 1 9
1 2 3 4 D C 5 6 7 0
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 4/ 8( 50%) 0/16( 0%) 6/36( 16%)
B: LC17 - LC32 2/16( 12%) 8/ 8(100%) 0/16( 0%) 6/36( 16%)
C: LC33 - LC48 4/16( 25%) 8/ 8(100%) 0/16( 0%) 6/36( 16%)
D: LC49 - LC64 12/16( 75%) 8/ 8(100%) 0/16( 0%) 12/36( 33%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 28/32 ( 87%)
Total logic cells used: 21/64 ( 32%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 21/64 ( 32%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 5.28
Total fan-in: 111
Total input pins required: 10
Total fast input logic cells required: 0
Total output pins required: 16
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 21
Total flipflops required: 0
Total product terms required: 31
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT 0 0 0 0 0 0 5 ALE
17 (24) (B) INPUT 0 0 0 0 0 0 1 P00
18 (21) (B) INPUT 0 0 0 0 0 0 1 P01
19 (20) (B) INPUT 0 0 0 0 0 0 1 P02
20 (19) (B) INPUT 0 0 0 0 0 0 1 P03
21 (17) (B) INPUT 0 0 0 0 0 0 1 P04
24 (33) (C) INPUT 0 0 0 0 0 0 0 P05
25 (35) (C) INPUT 0 0 0 0 0 0 0 P06
26 (36) (C) INPUT 0 0 0 0 0 0 0 P07
1 - - INPUT 0 0 0 0 0 16 0 P27
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
40 62 D OUTPUT t 0 0 0 1 5 0 0 Y0
41 64 D OUTPUT t 0 0 0 1 5 0 0 Y1
34 51 D OUTPUT t 0 0 0 1 5 0 0 Y2
36 52 D OUTPUT t 0 0 0 1 5 0 0 Y3
39 57 D OUTPUT t 0 0 0 1 5 0 0 Y4
37 53 D OUTPUT t 0 0 0 1 5 0 0 Y5
33 49 D OUTPUT t 0 0 0 1 5 0 0 Y6
31 46 C OUTPUT t 0 0 0 1 5 0 0 Y7
29 41 C OUTPUT t 0 0 0 1 5 0 0 Y8
28 40 C OUTPUT t 0 0 0 1 5 0 0 Y9
27 37 C OUTPUT t 0 0 0 1 5 0 0 Y10
14 30 B OUTPUT t 0 0 0 1 5 0 0 Y11
16 25 B OUTPUT t 0 0 0 1 5 0 0 Y12
11 3 A OUTPUT t 0 0 0 1 5 0 0 Y13
12 1 A OUTPUT t 0 0 0 1 5 0 0 Y14
9 4 A OUTPUT t 0 0 0 1 5 0 0 Y15
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D LCELL t 0 0 0 2 1 16 1 |74373:112|:12
- 55 D LCELL t 0 0 0 2 1 16 1 |74373:112|:13
- 54 D LCELL t 0 0 0 2 1 16 1 |74373:112|:14
(38) 56 D LCELL t 0 0 0 2 1 16 1 |74373:112|:15
- 58 D LCELL t 0 0 0 2 1 16 1 |74373:112|:16
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC3 Y13
| +--- LC1 Y14
| | +- LC4 Y15
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D | Logic cells that feed LAB 'A':
Pin
43 -> - - - | - - - * | <-- ALE
1 -> * * * | * * * * | <-- P27
LC50 -> * * * | * * * * | <-- |74373:112|:12
LC55 -> * * * | * * * * | <-- |74373:112|:13
LC54 -> * * * | * * * * | <-- |74373:112|:14
LC56 -> * * * | * * * * | <-- |74373:112|:15
LC58 -> * * * | * * * * | <-- |74373:112|:16
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC30 Y11
| +- LC25 Y12
| |
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