?? mcu_ctrl.rpt
字號:
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D | Logic cells that feed LAB 'B':
Pin
43 -> - - | - - - * | <-- ALE
1 -> * * | * * * * | <-- P27
LC50 -> * * | * * * * | <-- |74373:112|:12
LC55 -> * * | * * * * | <-- |74373:112|:13
LC54 -> * * | * * * * | <-- |74373:112|:14
LC56 -> * * | * * * * | <-- |74373:112|:15
LC58 -> * * | * * * * | <-- |74373:112|:16
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------- LC46 Y7
| +----- LC41 Y8
| | +--- LC40 Y9
| | | +- LC37 Y10
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'C'
LC | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
43 -> - - - - | - - - * | <-- ALE
1 -> * * * * | * * * * | <-- P27
LC50 -> * * * * | * * * * | <-- |74373:112|:12
LC55 -> * * * * | * * * * | <-- |74373:112|:13
LC54 -> * * * * | * * * * | <-- |74373:112|:14
LC56 -> * * * * | * * * * | <-- |74373:112|:15
LC58 -> * * * * | * * * * | <-- |74373:112|:16
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------- LC62 Y0
| +--------------------- LC64 Y1
| | +------------------- LC51 Y2
| | | +----------------- LC52 Y3
| | | | +--------------- LC57 Y4
| | | | | +------------- LC53 Y5
| | | | | | +----------- LC49 Y6
| | | | | | | +--------- LC50 |74373:112|:12
| | | | | | | | +------- LC55 |74373:112|:13
| | | | | | | | | +----- LC54 |74373:112|:14
| | | | | | | | | | +--- LC56 |74373:112|:15
| | | | | | | | | | | +- LC58 |74373:112|:16
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC50 -> * * * * * * * * - - - - | * * * * | <-- |74373:112|:12
LC55 -> * * * * * * * - * - - - | * * * * | <-- |74373:112|:13
LC54 -> * * * * * * * - - * - - | * * * * | <-- |74373:112|:14
LC56 -> * * * * * * * - - - * - | * * * * | <-- |74373:112|:15
LC58 -> * * * * * * * - - - - * | * * * * | <-- |74373:112|:16
Pin
43 -> - - - - - - - * * * * * | - - - * | <-- ALE
17 -> - - - - - - - * - - - - | - - - * | <-- P00
18 -> - - - - - - - - * - - - | - - - * | <-- P01
19 -> - - - - - - - - - * - - | - - - * | <-- P02
20 -> - - - - - - - - - - * - | - - - * | <-- P03
21 -> - - - - - - - - - - - * | - - - * | <-- P04
1 -> * * * * * * * - - - - - | * * * * | <-- P27
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\mcu_ctrl.rpt
mcu_ctrl
** EQUATIONS **
ALE : INPUT;
P00 : INPUT;
P01 : INPUT;
P02 : INPUT;
P03 : INPUT;
P04 : INPUT;
P05 : INPUT;
P06 : INPUT;
P07 : INPUT;
P27 : INPUT;
-- Node name is 'Y0'
-- Equation name is 'Y0', location is LC062, type is output.
Y0 = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC050 & !_LC054 & !_LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y1'
-- Equation name is 'Y1', location is LC064, type is output.
Y1 = LCELL( _EQ002 $ VCC);
_EQ002 = _LC050 & !_LC054 & !_LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y2'
-- Equation name is 'Y2', location is LC051, type is output.
Y2 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC050 & !_LC054 & _LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y3'
-- Equation name is 'Y3', location is LC052, type is output.
Y3 = LCELL( _EQ004 $ VCC);
_EQ004 = _LC050 & !_LC054 & _LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y4'
-- Equation name is 'Y4', location is LC057, type is output.
Y4 = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC050 & _LC054 & !_LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y5'
-- Equation name is 'Y5', location is LC053, type is output.
Y5 = LCELL( _EQ006 $ VCC);
_EQ006 = _LC050 & _LC054 & !_LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y6'
-- Equation name is 'Y6', location is LC049, type is output.
Y6 = LCELL( _EQ007 $ VCC);
_EQ007 = !_LC050 & _LC054 & _LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y7'
-- Equation name is 'Y7', location is LC046, type is output.
Y7 = LCELL( _EQ008 $ VCC);
_EQ008 = _LC050 & _LC054 & _LC055 & !_LC056 & !_LC058 & P27;
-- Node name is 'Y8'
-- Equation name is 'Y8', location is LC041, type is output.
Y8 = LCELL( _EQ009 $ VCC);
_EQ009 = !_LC050 & !_LC054 & !_LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y9'
-- Equation name is 'Y9', location is LC040, type is output.
Y9 = LCELL( _EQ010 $ VCC);
_EQ010 = _LC050 & !_LC054 & !_LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y10'
-- Equation name is 'Y10', location is LC037, type is output.
Y10 = LCELL( _EQ011 $ VCC);
_EQ011 = !_LC050 & !_LC054 & _LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y11'
-- Equation name is 'Y11', location is LC030, type is output.
Y11 = LCELL( _EQ012 $ VCC);
_EQ012 = _LC050 & !_LC054 & _LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y12'
-- Equation name is 'Y12', location is LC025, type is output.
Y12 = LCELL( _EQ013 $ VCC);
_EQ013 = !_LC050 & _LC054 & !_LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y13'
-- Equation name is 'Y13', location is LC003, type is output.
Y13 = LCELL( _EQ014 $ VCC);
_EQ014 = _LC050 & _LC054 & !_LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y14'
-- Equation name is 'Y14', location is LC001, type is output.
Y14 = LCELL( _EQ015 $ VCC);
_EQ015 = !_LC050 & _LC054 & _LC055 & _LC056 & !_LC058 & P27;
-- Node name is 'Y15'
-- Equation name is 'Y15', location is LC004, type is output.
Y15 = LCELL( _EQ016 $ VCC);
_EQ016 = _LC050 & _LC054 & _LC055 & _LC056 & !_LC058 & P27;
-- Node name is '|74373:112|:12'
-- Equation name is '_LC050', type is buried
_LC050 = LCELL( _EQ017 $ GND);
_EQ017 = ALE & P00
# _LC050 & P00
# !ALE & _LC050;
-- Node name is '|74373:112|:13'
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( _EQ018 $ GND);
_EQ018 = ALE & P01
# _LC055 & P01
# !ALE & _LC055;
-- Node name is '|74373:112|:14'
-- Equation name is '_LC054', type is buried
_LC054 = LCELL( _EQ019 $ GND);
_EQ019 = ALE & P02
# _LC054 & P02
# !ALE & _LC054;
-- Node name is '|74373:112|:15'
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( _EQ020 $ GND);
_EQ020 = ALE & P03
# _LC056 & P03
# !ALE & _LC056;
-- Node name is '|74373:112|:16'
-- Equation name is '_LC058', type is buried
_LC058 = LCELL( _EQ021 $ GND);
_EQ021 = ALE & P04
# _LC058 & P04
# !ALE & _LC058;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\fast_adc\mcu_ctrl.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,150K
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