module example_b(input wire clk, rst, input_sig_1, input_sig_2,
                 output reg a, b);
parameter S0 = 2'h0, S1 = 2'h1, S2 = 2'h2;
reg [1:0] state, next_state;
always @ (posedge clk)
    if (rst) // Fully synchronous reset
        state <= #1 S0;
    else
        state <= #1 next_state;
always @ (state or input_sig_1 or input_sig_2 )
begin
    a = 1'b0;
    b = 1'b0;
    next_state = S0; // FSM will default to the S0 state
    case (state)
        S0: begin
            if (input_sig_1 || input_sig_2)
                a = 1'b1;
            if(input_sig_1 == 1'b1)
                next_state = S1;
        end
        S1: begin
            b = 1'b1;
            if(input_sig_2 == 1'b1)
                next_state = S2;
        end
        S2: ; // do nothing
        default: begin
            a = 1'bx;
            b = 1'bx;
        end
    endcase
end
endmodule