/*    Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver    Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>    Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>    This program is free software; you can redistribute it and/or modify    it under the terms of the GNU General Public License as published by    the Free Software Foundation; either version 2 of the License, or    (at your option) any later version.    This program is distributed in the hope that it will be useful,    but WITHOUT ANY WARRANTY; without even the implied warranty of    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    GNU General Public License for more details.    You should have received a copy of the GNU General Public License    along with this program; if not, write to the Free Software    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.*/#include <linux/slab.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/moduleparam.h>#include <linux/init.h>#include "dvb_frontend.h"#include "cx24123.h"#define XTAL 10111000static int force_band;static int debug;#define dprintk(args...) \	do { \		if (debug) printk (KERN_DEBUG "cx24123: " args); \	} while (0)struct cx24123_state{	struct i2c_adapter* i2c;	struct dvb_frontend_ops ops;	const struct cx24123_config* config;	struct dvb_frontend frontend;	u32 lastber;	u16 snr;	u8  lnbreg;	/* Some PLL specifics for tuning */	u32 VCAarg;	u32 VGAarg;	u32 bandselectarg;	u32 pllarg;	u32 FILTune;	/* The Demod/Tuner can't easily provide these, we cache them */	u32 currentfreq;	u32 currentsymbolrate;};/* Various tuner defaults need to be established for a given symbol rate Sps */static struct{	u32 symbolrate_low;	u32 symbolrate_high;	u32 VCAprogdata;	u32 VGAprogdata;	u32 FILTune;} cx24123_AGC_vals[] ={	{		.symbolrate_low		= 1000000,		.symbolrate_high	= 4999999,		/* the specs recommend other values for VGA offsets,		   but tests show they are wrong */		.VGAprogdata		= (1 << 19) | (0x180 << 9) | 0x1e0,		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x07,		.FILTune		= 0x27f /* 0.41 V */	},	{		.symbolrate_low		=  5000000,		.symbolrate_high	= 14999999,		.VGAprogdata		= (1 << 19) | (0x180 << 9) | 0x1e0,		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x1f,		.FILTune		= 0x317 /* 0.90 V */	},	{		.symbolrate_low		= 15000000,		.symbolrate_high	= 45000000,		.VGAprogdata		= (1 << 19) | (0x100 << 9) | 0x180,		.VCAprogdata		= (2 << 19) | (0x07 << 9) | 0x3f,		.FILTune		= 0x145 /* 2.70 V */	},};/* * Various tuner defaults need to be established for a given frequency kHz. * fixme: The bounds on the bands do not match the doc in real life. * fixme: Some of them have been moved, other might need adjustment. */static struct{	u32 freq_low;	u32 freq_high;	u32 VCOdivider;	u32 progdata;} cx24123_bandselect_vals[] ={	/* band 1 */	{		.freq_low	= 950000,		.freq_high	= 1074999,		.VCOdivider	= 4,		.progdata	= (0 << 19) | (0 << 9) | 0x40,	},	/* band 2 */	{		.freq_low	= 1075000,		.freq_high	= 1177999,		.VCOdivider	= 4,		.progdata	= (0 << 19) | (0 << 9) | 0x80,	},	/* band 3 */	{		.freq_low	= 1178000,		.freq_high	= 1295999,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x01,	},	/* band 4 */	{		.freq_low	= 1296000,		.freq_high	= 1431999,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x02,	},	/* band 5 */	{		.freq_low	= 1432000,		.freq_high	= 1575999,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x04,	},	/* band 6 */	{		.freq_low	= 1576000,		.freq_high	= 1717999,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x08,	},	/* band 7 */	{		.freq_low	= 1718000,		.freq_high	= 1855999,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x10,	},	/* band 8 */	{		.freq_low	= 1856000,		.freq_high	= 2035999,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x20,	},	/* band 9 */	{		.freq_low	= 2036000,		.freq_high	= 2150000,		.VCOdivider	= 2,		.progdata	= (0 << 19) | (1 << 9) | 0x40,	},};static struct {	u8 reg;	u8 data;} cx24123_regdata[] ={	{0x00, 0x03}, /* Reset system */	{0x00, 0x00}, /* Clear reset */	{0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */	{0x04, 0x10}, /* MPEG */	{0x05, 0x04}, /* MPEG */	{0x06, 0x31}, /* MPEG (default) */	{0x0b, 0x00}, /* Freq search start point (default) */	{0x0c, 0x00}, /* Demodulator sample gain (default) */	{0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */	{0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */	{0x0f, 0xfe}, /* FEC search mask (all supported codes) */	{0x10, 0x01}, /* Default search inversion, no repeat (default) */	{0x16, 0x00}, /* Enable reading of frequency */	{0x17, 0x01}, /* Enable EsNO Ready Counter */	{0x1c, 0x80}, /* Enable error counter */	{0x20, 0x00}, /* Tuner burst clock rate = 500KHz */	{0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */	{0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */	{0x29, 0x00}, /* DiSEqC LNB_DC off */	{0x2a, 0xb0}, /* DiSEqC Parameters (default) */	{0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */	{0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */	{0x2d, 0x00},	{0x2e, 0x00},	{0x2f, 0x00},	{0x30, 0x00},	{0x31, 0x00},	{0x32, 0x8c}, /* DiSEqC Parameters (default) */	{0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */	{0x34, 0x00},	{0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */	{0x36, 0x02}, /* DiSEqC Parameters (default) */	{0x37, 0x3a}, /* DiSEqC Parameters (default) */	{0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */	{0x44, 0x00}, /* Constellation (default) */	{0x45, 0x00}, /* Symbol count (default) */	{0x46, 0x0d}, /* Symbol rate estimator on (default) */	{0x56, 0x41}, /* Various (default) */	{0x57, 0xff}, /* Error Counter Window (default) */	{0x67, 0x83}, /* Non-DCII symbol clock */};static int cx24123_writereg(struct cx24123_state* state, int reg, int data){	u8 buf[] = { reg, data };	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };	int err;	if (debug>1)		printk("cx24123: %s:  write reg 0x%02x, value 0x%02x\n",						__FUNCTION__,reg, data);	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {		printk("%s: writereg error(err == %i, reg == 0x%02x,"			 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);		return -EREMOTEIO;	}	return 0;}static int cx24123_writelnbreg(struct cx24123_state* state, int reg, int data){	u8 buf[] = { reg, data };	/* fixme: put the intersil addr int the config */	struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 2 };	int err;	if (debug>1)		printk("cx24123: %s:  writeln addr=0x08, reg 0x%02x, value 0x%02x\n",						__FUNCTION__,reg, data);	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {		printk("%s: writelnbreg error (err == %i, reg == 0x%02x,"			 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);		return -EREMOTEIO;	}	/* cache the write, no way to read back */	state->lnbreg = data;	return 0;}static int cx24123_readreg(struct cx24123_state* state, u8 reg){	int ret;	u8 b0[] = { reg };	u8 b1[] = { 0 };	struct i2c_msg msg[] = {		{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },		{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }	};	ret = i2c_transfer(state->i2c, msg, 2);	if (ret != 2) {		printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);		return ret;	}	if (debug>1)		printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);	return b1[0];}static int cx24123_readlnbreg(struct cx24123_state* state, u8 reg){	return state->lnbreg;}static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion){	u8 nom_reg = cx24123_readreg(state, 0x0e);	u8 auto_reg = cx24123_readreg(state, 0x10);	switch (inversion) {	case INVERSION_OFF:		dprintk("%s:  inversion off\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg & ~0x80);		cx24123_writereg(state, 0x10, auto_reg | 0x80);		break;	case INVERSION_ON:		dprintk("%s:  inversion on\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x80);		cx24123_writereg(state, 0x10, auto_reg | 0x80);		break;	case INVERSION_AUTO:		dprintk("%s:  inversion auto\n",__FUNCTION__);		cx24123_writereg(state, 0x10, auto_reg & ~0x80);		break;	default:		return -EINVAL;	}	return 0;}static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion){	u8 val;	val = cx24123_readreg(state, 0x1b) >> 7;	if (val == 0) {		dprintk("%s:  read inversion off\n",__FUNCTION__);		*inversion = INVERSION_OFF;	} else {		dprintk("%s:  read inversion on\n",__FUNCTION__);		*inversion = INVERSION_ON;	}	return 0;}static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec){	u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;	if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )		fec = FEC_AUTO;	switch (fec) {	case FEC_1_2:		dprintk("%s:  set FEC to 1/2\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x01);		cx24123_writereg(state, 0x0f, 0x02);		break;	case FEC_2_3:		dprintk("%s:  set FEC to 2/3\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x02);		cx24123_writereg(state, 0x0f, 0x04);		break;	case FEC_3_4:		dprintk("%s:  set FEC to 3/4\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x03);		cx24123_writereg(state, 0x0f, 0x08);		break;	case FEC_4_5:		dprintk("%s:  set FEC to 4/5\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x04);		cx24123_writereg(state, 0x0f, 0x10);		break;	case FEC_5_6:		dprintk("%s:  set FEC to 5/6\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x05);		cx24123_writereg(state, 0x0f, 0x20);		break;	case FEC_6_7:		dprintk("%s:  set FEC to 6/7\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x06);		cx24123_writereg(state, 0x0f, 0x40);		break;	case FEC_7_8:		dprintk("%s:  set FEC to 7/8\n",__FUNCTION__);		cx24123_writereg(state, 0x0e, nom_reg | 0x07);		cx24123_writereg(state, 0x0f, 0x80);		break;	case FEC_AUTO:		dprintk("%s:  set FEC to auto\n",__FUNCTION__);		cx24123_writereg(state, 0x0f, 0xfe);		break;	default:		return -EOPNOTSUPP;	}	return 0;}static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec){	int ret;	ret = cx24123_readreg (state, 0x1b);	if (ret < 0)		return ret;	ret = ret & 0x07;	switch (ret) {	case 1:		*fec = FEC_1_2;		break;	case 2:		*fec = FEC_2_3;		break;	case 3:		*fec = FEC_3_4;		break;	case 4:		*fec = FEC_4_5;		break;	case 5:		*fec = FEC_5_6;		break;	case 6:		*fec = FEC_6_7;		break;	case 7:		*fec = FEC_7_8;		break;	default:		/* this can happen when there's no lock */		*fec = FEC_NONE;	}	return 0;}/* Approximation of closest integer of log2(a/b). It actually gives the   lowest integer i such that 2^i >= round(a/b) */static u32 cx24123_int_log2(u32 a, u32 b){	u32 exp, nearest = 0;	u32 div = a / b;	if(a % b >= b / 2) ++div;	if(div < (1 << 31))	{		for(exp = 1; div > exp; nearest++)			exp += exp;	}	return nearest;}static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate){	u32 tmp, sample_rate, ratio, sample_gain;	u8 pll_mult;	/*  check if symbol rate is within limits */	if ((srate > state->ops.info.symbol_rate_max) ||	    (srate < state->ops.info.symbol_rate_min))		return -EOPNOTSUPP;;	/* choose the sampling rate high enough for the required operation,	   while optimizing the power consumed by the demodulator */	if (srate < (XTAL*2)/2)		pll_mult = 2;	else if (srate < (XTAL*3)/2)		pll_mult = 3;	else if (srate < (XTAL*4)/2)		pll_mult = 4;	else if (srate < (XTAL*5)/2)		pll_mult = 5;	else if (srate < (XTAL*6)/2)		pll_mult = 6;	else if (srate < (XTAL*7)/2)		pll_mult = 7;	else if (srate < (XTAL*8)/2)		pll_mult = 8;	else		pll_mult = 9;	sample_rate = pll_mult * XTAL;	/*	    SYSSymbolRate[21:0] = (srate << 23) / sample_rate	    We have to use 32 bit unsigned arithmetic without precision loss.	    The maximum srate is 45000000 or 0x02AEA540. This number has	    only 6 clear bits on top, hence we can shift it left only 6 bits	    at a time. Borrowed from cx24110.c	*/	tmp = srate << 6;	ratio = tmp / sample_rate;	tmp = (tmp % sample_rate) << 6;	ratio = (ratio << 6) + (tmp / sample_rate);	tmp = (tmp % sample_rate) << 6;	ratio = (ratio << 6) + (tmp / sample_rate);	tmp = (tmp % sample_rate) << 5;	ratio = (ratio << 5) + (tmp / sample_rate);	cx24123_writereg(state, 0x01, pll_mult * 6);	cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );	cx24123_writereg(state, 0x09, (ratio >>  8) & 0xff );	cx24123_writereg(state, 0x0a, (ratio      ) & 0xff );	/* also set the demodulator sample gain */	sample_gain = cx24123_int_log2(sample_rate, srate);	tmp = cx24123_readreg(state, 0x0c) & ~0xe0;	cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);	dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain);	return 0;}/* * Based on the required frequency and symbolrate, the tuner AGC has to be configured * and the correct band selected. Calculate those values */static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p){	struct cx24123_state *state = fe->demodulator_priv;	u32 ndiv = 0, adiv = 0, vco_div = 0;	int i = 0;	int pump = 2;	int band = 0;	int num_bands = sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]);	/* Defaults for low freq, low rate */	state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;	state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;	state->bandselectarg = cx24123_bandselect_vals[0].progdata;	vco_div = cx24123_bandselect_vals[0].VCOdivider;	/* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */	for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)	{		if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&		    (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {			state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;			state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;			state->FILTune = cx24123_AGC_vals[i].FILTune;		}	}	/* determine the band to use */	if(force_band < 1 || force_band > num_bands)	{		for (i = 0; i < num_bands; i++)		{