/*** -*- linux-c -*- **********************************************************     Driver for Atmel at76c502 at76c504 and at76c506 wireless cards.        Copyright 2000-2001 ATMEL Corporation.        Copyright 2003-2004 Simon Kelley.    This code was developed from version 2.1.1 of the Atmel drivers,    released by Atmel corp. under the GPL in December 2002. It also    includes code from the Linux aironet drivers (C) Benjamin Reed,    and the Linux PCMCIA package, (C) David Hinds and the Linux wireless    extensions, (C) Jean Tourrilhes.    The firmware module for reading the MAC address of the card comes from    net.russotto.AtmelMACFW, written by Matthew T. Russotto and copyright    by him. net.russotto.AtmelMACFW is used under the GPL license version 2.    This file contains the module in binary form and, under the terms    of the GPL, in source form. The source is located at the end of the file.    This program is free software; you can redistribute it and/or modify    it under the terms of the GNU General Public License as published by    the Free Software Foundation; either version 2 of the License, or    (at your option) any later version.    This software is distributed in the hope that it will be useful,    but WITHOUT ANY WARRANTY; without even the implied warranty of    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    GNU General Public License for more details.    You should have received a copy of the GNU General Public License    along with Atmel wireless lan drivers; if not, write to the Free Software    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA    For all queries about this code, please contact the current author,    Simon Kelley <simon@thekelleys.org.uk> and not Atmel Corporation.    Credit is due to HP UK and Cambridge Online Systems Ltd for supplying    hardware used during development of this driver.******************************************************************************/#include <linux/config.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/ptrace.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/ctype.h>#include <linux/timer.h>#include <asm/io.h>#include <asm/system.h>#include <asm/uaccess.h>#include <linux/module.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/if_arp.h>#include <linux/ioport.h>#include <linux/fcntl.h>#include <linux/delay.h>#include <linux/wireless.h>#include <net/iw_handler.h>#include <linux/byteorder/generic.h>#include <linux/crc32.h>#include <linux/proc_fs.h>#include <linux/device.h>#include <linux/moduleparam.h>#include <linux/firmware.h>#include <net/ieee80211.h>#include "atmel.h"#define DRIVER_MAJOR 0#define DRIVER_MINOR 98MODULE_AUTHOR("Simon Kelley");MODULE_DESCRIPTION("Support for Atmel at76c50x 802.11 wireless ethernet cards.");MODULE_LICENSE("GPL");MODULE_SUPPORTED_DEVICE("Atmel at76c50x wireless cards");/* The name of the firmware file to be loaded   over-rides any automatic selection */static char *firmware = NULL;module_param(firmware, charp, 0);/* table of firmware file names */static struct {	AtmelFWType fw_type;	const char *fw_file;	const char *fw_file_ext;} fw_table[] = {	{ ATMEL_FW_TYPE_502,      "atmel_at76c502",      "bin" },	{ ATMEL_FW_TYPE_502D,     "atmel_at76c502d",     "bin" },	{ ATMEL_FW_TYPE_502E,     "atmel_at76c502e",     "bin" },	{ ATMEL_FW_TYPE_502_3COM, "atmel_at76c502_3com", "bin" },	{ ATMEL_FW_TYPE_504,      "atmel_at76c504",      "bin" },	{ ATMEL_FW_TYPE_504_2958, "atmel_at76c504_2958", "bin" },	{ ATMEL_FW_TYPE_504A_2958,"atmel_at76c504a_2958","bin" },	{ ATMEL_FW_TYPE_506,      "atmel_at76c506",      "bin" },	{ ATMEL_FW_TYPE_NONE,      NULL,                  NULL }};#define MAX_SSID_LENGTH 32#define MGMT_JIFFIES (256 * HZ / 100)#define MAX_BSS_ENTRIES	64/* registers */#define GCR  0x00    //      (SIR0)  General Configuration Register#define BSR  0x02    //      (SIR1)  Bank Switching Select Register#define AR   0x04#define DR   0x08#define MR1  0x12    //      Mirror Register 1#define MR2  0x14    //      Mirror Register 2#define MR3  0x16    //      Mirror Register 3#define MR4  0x18    //      Mirror Register 4#define GPR1                            0x0c#define GPR2                            0x0e#define GPR3                            0x10//// Constants for the GCR register.//#define GCR_REMAP     0x0400          // Remap internal SRAM to 0#define GCR_SWRES     0x0080          // BIU reset (ARM and PAI are NOT reset)#define GCR_CORES     0x0060          // Core Reset (ARM and PAI are reset)#define GCR_ENINT     0x0002          // Enable Interrupts#define GCR_ACKINT    0x0008          // Acknowledge Interrupts#define BSS_SRAM      0x0200          // AMBA module selection --> SRAM#define BSS_IRAM      0x0100          // AMBA module selection --> IRAM//// Constants for the MR registers.//#define MAC_INIT_COMPLETE       0x0001        // MAC init has been completed#define MAC_BOOT_COMPLETE       0x0010        // MAC boot has been completed#define MAC_INIT_OK             0x0002        // MAC boot has been completed#define MIB_MAX_DATA_BYTES    212#define MIB_HEADER_SIZE       4    /* first four fields */struct get_set_mib {        u8 type;        u8 size;        u8 index;        u8 reserved;        u8 data[MIB_MAX_DATA_BYTES];};struct rx_desc {        u32          Next;        u16          MsduPos;        u16          MsduSize;        u8           State;        u8           Status;        u8           Rate;        u8           Rssi;        u8           LinkQuality;        u8           PreambleType;        u16          Duration;        u32          RxTime;};#define RX_DESC_FLAG_VALID       0x80#define RX_DESC_FLAG_CONSUMED    0x40#define RX_DESC_FLAG_IDLE        0x00#define RX_STATUS_SUCCESS        0x00#define RX_DESC_MSDU_POS_OFFSET      4#define RX_DESC_MSDU_SIZE_OFFSET     6#define RX_DESC_FLAGS_OFFSET         8#define RX_DESC_STATUS_OFFSET        9#define RX_DESC_RSSI_OFFSET          11#define RX_DESC_LINK_QUALITY_OFFSET  12#define RX_DESC_PREAMBLE_TYPE_OFFSET 13#define RX_DESC_DURATION_OFFSET      14#define RX_DESC_RX_TIME_OFFSET       16struct tx_desc {	u32       NextDescriptor;	u16       TxStartOfFrame;	u16       TxLength;	u8        TxState;	u8        TxStatus;	u8        RetryCount;	u8        TxRate;	u8        KeyIndex;	u8        ChiperType;	u8        ChipreLength;        u8        Reserved1;	u8        Reserved;	u8        PacketType;	u16       HostTxLength;};#define TX_DESC_NEXT_OFFSET          0#define TX_DESC_POS_OFFSET           4#define TX_DESC_SIZE_OFFSET          6#define TX_DESC_FLAGS_OFFSET         8#define TX_DESC_STATUS_OFFSET        9#define TX_DESC_RETRY_OFFSET         10#define TX_DESC_RATE_OFFSET          11#define TX_DESC_KEY_INDEX_OFFSET     12#define TX_DESC_CIPHER_TYPE_OFFSET   13#define TX_DESC_CIPHER_LENGTH_OFFSET 14#define TX_DESC_PACKET_TYPE_OFFSET   17#define TX_DESC_HOST_LENGTH_OFFSET   18///////////////////////////////////////////////////////// Host-MAC interface///////////////////////////////////////////////////////#define TX_STATUS_SUCCESS       0x00#define TX_FIRM_OWN             0x80#define TX_DONE                 0x40#define TX_ERROR                0x01#define TX_PACKET_TYPE_DATA     0x01#define TX_PACKET_TYPE_MGMT     0x02#define ISR_EMPTY               0x00        // no bits set in ISR#define ISR_TxCOMPLETE          0x01        // packet transmitted#define ISR_RxCOMPLETE          0x02        // packet received#define ISR_RxFRAMELOST         0x04        // Rx Frame lost#define ISR_FATAL_ERROR         0x08        // Fatal error#define ISR_COMMAND_COMPLETE    0x10        // command completed#define ISR_OUT_OF_RANGE        0x20        // command completed#define ISR_IBSS_MERGE          0x40        // (4.1.2.30): IBSS merge#define ISR_GENERIC_IRQ         0x80#define Local_Mib_Type          0x01#define Mac_Address_Mib_Type    0x02#define Mac_Mib_Type            0x03#define Statistics_Mib_Type     0x04#define Mac_Mgmt_Mib_Type       0x05#define Mac_Wep_Mib_Type        0x06#define Phy_Mib_Type            0x07#define Multi_Domain_MIB        0x08#define MAC_MGMT_MIB_CUR_BSSID_POS            14#define MAC_MIB_FRAG_THRESHOLD_POS            8#define MAC_MIB_RTS_THRESHOLD_POS             10#define MAC_MIB_SHORT_RETRY_POS               16#define MAC_MIB_LONG_RETRY_POS                17#define MAC_MIB_SHORT_RETRY_LIMIT_POS         16#define MAC_MGMT_MIB_BEACON_PER_POS           0#define MAC_MGMT_MIB_STATION_ID_POS           6#define MAC_MGMT_MIB_CUR_PRIVACY_POS          11#define MAC_MGMT_MIB_CUR_BSSID_POS            14#define MAC_MGMT_MIB_PS_MODE_POS              53#define MAC_MGMT_MIB_LISTEN_INTERVAL_POS      54#define MAC_MGMT_MIB_MULTI_DOMAIN_IMPLEMENTED 56#define MAC_MGMT_MIB_MULTI_DOMAIN_ENABLED     57#define PHY_MIB_CHANNEL_POS                   14#define PHY_MIB_RATE_SET_POS                  20#define PHY_MIB_REG_DOMAIN_POS                26#define LOCAL_MIB_AUTO_TX_RATE_POS            3#define LOCAL_MIB_SSID_SIZE                   5#define LOCAL_MIB_TX_PROMISCUOUS_POS          6#define LOCAL_MIB_TX_MGMT_RATE_POS            7#define LOCAL_MIB_TX_CONTROL_RATE_POS         8#define LOCAL_MIB_PREAMBLE_TYPE               9#define MAC_ADDR_MIB_MAC_ADDR_POS             0#define         CMD_Set_MIB_Vars              0x01#define         CMD_Get_MIB_Vars              0x02#define         CMD_Scan                      0x03#define         CMD_Join                      0x04#define         CMD_Start                     0x05#define         CMD_EnableRadio               0x06#define         CMD_DisableRadio              0x07#define         CMD_SiteSurvey                0x0B#define         CMD_STATUS_IDLE                   0x00#define         CMD_STATUS_COMPLETE               0x01#define         CMD_STATUS_UNKNOWN                0x02#define         CMD_STATUS_INVALID_PARAMETER      0x03#define         CMD_STATUS_FUNCTION_NOT_SUPPORTED 0x04#define         CMD_STATUS_TIME_OUT               0x07#define         CMD_STATUS_IN_PROGRESS            0x08#define         CMD_STATUS_REJECTED_RADIO_OFF     0x09#define         CMD_STATUS_HOST_ERROR             0xFF#define         CMD_STATUS_BUSY                   0xFE#define CMD_BLOCK_COMMAND_OFFSET        0#define CMD_BLOCK_STATUS_OFFSET         1#define CMD_BLOCK_PARAMETERS_OFFSET     4#define SCAN_OPTIONS_SITE_SURVEY        0x80#define MGMT_FRAME_BODY_OFFSET		24#define MAX_AUTHENTICATION_RETRIES	3#define MAX_ASSOCIATION_RETRIES		3#define AUTHENTICATION_RESPONSE_TIME_OUT  1000#define MAX_WIRELESS_BODY  2316 /* mtu is 2312, CRC is 4 */#define LOOP_RETRY_LIMIT   500000#define ACTIVE_MODE	1#define PS_MODE		2#define MAX_ENCRYPTION_KEYS 4#define MAX_ENCRYPTION_KEY_SIZE 40///////////////////////////////////////////////////////////////////////////// 802.11 related definitions/////////////////////////////////////////////////////////////////////////////// Regulatory Domains//#define REG_DOMAIN_FCC		0x10	//Channels	1-11	USA#define REG_DOMAIN_DOC		0x20	//Channel	1-11	Canada#define REG_DOMAIN_ETSI		0x30	//Channel	1-13	Europe (ex Spain/France)#define REG_DOMAIN_SPAIN	0x31	//Channel	10-11	Spain#define REG_DOMAIN_FRANCE	0x32	//Channel	10-13	France#define REG_DOMAIN_MKK		0x40	//Channel	14	Japan#define REG_DOMAIN_MKK1		0x41	//Channel	1-14	Japan(MKK1)#define REG_DOMAIN_ISRAEL	0x50	//Channel	3-9	ISRAEL#define BSS_TYPE_AD_HOC		1#define BSS_TYPE_INFRASTRUCTURE 2#define SCAN_TYPE_ACTIVE	0#define SCAN_TYPE_PASSIVE	1#define LONG_PREAMBLE		0#define SHORT_PREAMBLE		1#define AUTO_PREAMBLE		2#define DATA_FRAME_WS_HEADER_SIZE   30/* promiscuous mode control */#define PROM_MODE_OFF			0x0#define PROM_MODE_UNKNOWN		0x1#define PROM_MODE_CRC_FAILED		0x2#define PROM_MODE_DUPLICATED		0x4#define PROM_MODE_MGMT			0x8#define PROM_MODE_CTRL			0x10#define PROM_MODE_BAD_PROTOCOL		0x20#define IFACE_INT_STATUS_OFFSET		0#define IFACE_INT_MASK_OFFSET		1#define IFACE_LOCKOUT_HOST_OFFSET	2#define IFACE_LOCKOUT_MAC_OFFSET	3#define IFACE_FUNC_CTRL_OFFSET		28#define IFACE_MAC_STAT_OFFSET		30#define IFACE_GENERIC_INT_TYPE_OFFSET	32#define CIPHER_SUITE_NONE     0#define CIPHER_SUITE_WEP_64   1#define CIPHER_SUITE_TKIP     2#define CIPHER_SUITE_AES      3#define CIPHER_SUITE_CCX      4#define CIPHER_SUITE_WEP_128  5//// IFACE MACROS & definitions////// FuncCtrl field://#define FUNC_CTRL_TxENABLE		0x10#define FUNC_CTRL_RxENABLE		0x20#define FUNC_CTRL_INIT_COMPLETE		0x01/* A stub firmware image which reads the MAC address from NVRAM on the card.   For copyright information and source see the end of this file. */static u8 mac_reader[] = {	0x06,0x00,0x00,0xea,0x04,0x00,0x00,0xea,0x03,0x00,0x00,0xea,0x02,0x00,0x00,0xea,	0x01,0x00,0x00,0xea,0x00,0x00,0x00,0xea,0xff,0xff,0xff,0xea,0xfe,0xff,0xff,0xea,	0xd3,0x00,0xa0,0xe3,0x00,0xf0,0x21,0xe1,0x0e,0x04,0xa0,0xe3,0x00,0x10,0xa0,0xe3,	0x81,0x11,0xa0,0xe1,0x00,0x10,0x81,0xe3,0x00,0x10,0x80,0xe5,0x1c,0x10,0x90,0xe5,	0x10,0x10,0xc1,0xe3,0x1c,0x10,0x80,0xe5,0x01,0x10,0xa0,0xe3,0x08,0x10,0x80,0xe5,	0x02,0x03,0xa0,0xe3,0x00,0x10,0xa0,0xe3,0xb0,0x10,0xc0,0xe1,0xb4,0x10,0xc0,0xe1,	0xb8,0x10,0xc0,0xe1,0xbc,0x10,0xc0,0xe1,0x56,0xdc,0xa0,0xe3,0x21,0x00,0x00,0xeb,	0x0a,0x00,0xa0,0xe3,0x1a,0x00,0x00,0xeb,0x10,0x00,0x00,0xeb,0x07,0x00,0x00,0xeb,	0x02,0x03,0xa0,0xe3,0x02,0x14,0xa0,0xe3,0xb4,0x10,0xc0,0xe1,0x4c,0x10,0x9f,0xe5,	0xbc,0x10,0xc0,0xe1,0x10,0x10,0xa0,0xe3,0xb8,0x10,0xc0,0xe1,0xfe,0xff,0xff,0xea,	0x00,0x40,0x2d,0xe9,0x00,0x20,0xa0,0xe3,0x02,0x3c,0xa0,0xe3,0x00,0x10,0xa0,0xe3,	0x28,0x00,0x9f,0xe5,0x37,0x00,0x00,0xeb,0x00,0x40,0xbd,0xe8,0x1e,0xff,0x2f,0xe1,	0x00,0x40,0x2d,0xe9,0x12,0x2e,0xa0,0xe3,0x06,0x30,0xa0,0xe3,0x00,0x10,0xa0,0xe3,	0x02,0x04,0xa0,0xe3,0x2f,0x00,0x00,0xeb,0x00,0x40,0xbd,0xe8,0x1e,0xff,0x2f,0xe1,	0x00,0x02,0x00,0x02,0x80,0x01,0x90,0xe0,0x01,0x00,0x00,0x0a,0x01,0x00,0x50,0xe2,	0xfc,0xff,0xff,0xea,0x1e,0xff,0x2f,0xe1,0x80,0x10,0xa0,0xe3,0xf3,0x06,0xa0,0xe3,	0x00,0x10,0x80,0xe5,0x00,0x10,0xa0,0xe3,0x00,0x10,0x80,0xe5,0x01,0x10,0xa0,0xe3,	0x04,0x10,0x80,0xe5,0x00,0x10,0x80,0xe5,0x0e,0x34,0xa0,0xe3,0x1c,0x10,0x93,0xe5,	0x02,0x1a,0x81,0xe3,0x1c,0x10,0x83,0xe5,0x58,0x11,0x9f,0xe5,0x30,0x10,0x80,0xe5,	0x54,0x11,0x9f,0xe5,0x34,0x10,0x80,0xe5,0x38,0x10,0x80,0xe5,0x3c,0x10,0x80,0xe5,	0x10,0x10,0x90,0xe5,0x08,0x00,0x90,0xe5,0x1e,0xff,0x2f,0xe1,0xf3,0x16,0xa0,0xe3,	0x08,0x00,0x91,0xe5,0x05,0x00,0xa0,0xe3,0x0c,0x00,0x81,0xe5,0x10,0x00,0x91,0xe5,	0x02,0x00,0x10,0xe3,0xfc,0xff,0xff,0x0a,0xff,0x00,0xa0,0xe3,0x0c,0x00,0x81,0xe5,	0x10,0x00,0x91,0xe5,0x02,0x00,0x10,0xe3,0xfc,0xff,0xff,0x0a,0x08,0x00,0x91,0xe5,	0x10,0x00,0x91,0xe5,0x01,0x00,0x10,0xe3,0xfc,0xff,0xff,0x0a,0x08,0x00,0x91,0xe5,	0xff,0x00,0x00,0xe2,0x1e,0xff,0x2f,0xe1,0x30,0x40,0x2d,0xe9,0x00,0x50,0xa0,0xe1,	0x03,0x40,0xa0,0xe1,0xa2,0x02,0xa0,0xe1,0x08,0x00,0x00,0xe2,0x03,0x00,0x80,0xe2,	0xd8,0x10,0x9f,0xe5,0x00,0x00,0xc1,0xe5,0x01,0x20,0xc1,0xe5,0xe2,0xff,0xff,0xeb,	0x01,0x00,0x10,0xe3,0xfc,0xff,0xff,0x1a,0x14,0x00,0xa0,0xe3,0xc4,0xff,0xff,0xeb,	0x04,0x20,0xa0,0xe1,0x05,0x10,0xa0,0xe1,0x02,0x00,0xa0,0xe3,0x01,0x00,0x00,0xeb,	0x30,0x40,0xbd,0xe8,0x1e,0xff,0x2f,0xe1,0x70,0x40,0x2d,0xe9,0xf3,0x46,0xa0,0xe3,	0x00,0x30,0xa0,0xe3,0x00,0x00,0x50,0xe3,0x08,0x00,0x00,0x9a,0x8c,0x50,0x9f,0xe5,	0x03,0x60,0xd5,0xe7,0x0c,0x60,0x84,0xe5,0x10,0x60,0x94,0xe5,0x02,0x00,0x16,0xe3,	0xfc,0xff,0xff,0x0a,0x01,0x30,0x83,0xe2,0x00,0x00,0x53,0xe1,0xf7,0xff,0xff,0x3a,	0xff,0x30,0xa0,0xe3,0x0c,0x30,0x84,0xe5,0x08,0x00,0x94,0xe5,0x10,0x00,0x94,0xe5,	0x01,0x00,0x10,0xe3,0xfc,0xff,0xff,0x0a,0x08,0x00,0x94,0xe5,0x00,0x00,0xa0,0xe3,	0x00,0x00,0x52,0xe3,0x0b,0x00,0x00,0x9a,0x10,0x50,0x94,0xe5,0x02,0x00,0x15,0xe3,	0xfc,0xff,0xff,0x0a,0x0c,0x30,0x84,0xe5,0x10,0x50,0x94,0xe5,0x01,0x00,0x15,0xe3,	0xfc,0xff,0xff,0x0a,0x08,0x50,0x94,0xe5,0x01,0x50,0xc1,0xe4,0x01,0x00,0x80,0xe2,	0x02,0x00,0x50,0xe1,0xf3,0xff,0xff,0x3a,0xc8,0x00,0xa0,0xe3,0x98,0xff,0xff,0xeb,	0x70,0x40,0xbd,0xe8,0x1e,0xff,0x2f,0xe1,0x01,0x0c,0x00,0x02,0x01,0x02,0x00,0x02,	0x00,0x01,0x00,0x02};struct atmel_private {	void *card; /* Bus dependent stucture varies for PCcard */	int (*present_callback)(void *); /* And callback which uses it */	char firmware_id[32];