?? gp32.h
字號(hào):
/* IO DEFINITIONS FOR MC68HC08
* Copyright (c) 1995 by COSMIC Software
*/
/* PORTS section
*/
@tiny volatile char PTA @0x00; /* port A Data Register*/
@tiny volatile char PTB @0x01; /* port B Data Register*/
//@tiny volatile char PTC @0x02; /* port C Data Register*/
@tiny volatile char PTD @0x03; /* port D Data Register*/
@tiny volatile char DDRA @0x04; /* data direction port A */
@tiny volatile char DDRB @0x05; /* data direction port B */
@tiny volatile char DDRC @0x06; /* data direction port C */
@tiny volatile char DDRD @0x07; /* data direction port D */
@tiny volatile char PTE @0x08; /* port E Data Register*/
@tiny volatile char DDRE @0x0c; /* data direction Register E */
@tiny volatile char PTAPUE @0x0d; /* Port A Input Pullup Enable Register */
@tiny volatile char PTCPUE @0x0e; /* Port C Input Pullup Enable Register */
@tiny volatile char PTDPUE @0x0f; /* Port D Input Pullup Enable Register */
/* SPI section
*/
@tiny volatile char SPCR @0x10; /* SPI control register */
@tiny volatile char SPSCR @0x11; /* SPI control/status register */
@tiny volatile char SPDR @0x12; /* SPI data register */
/* SCI section
*/
@tiny volatile char SCC1 @0x13; /* SCI control register 1 */
@tiny volatile char SCC2 @0x14; /* SCI control register 2 */
@tiny volatile char SCC3 @0x15; /* SCI control register 3 */
@tiny volatile char SCS1 @0x16; /* SCI status register 1 */
@tiny volatile char SCS2 @0x17; /* SCI status register 2 */
@tiny volatile char SCDR @0x18; /* SCI data register */
@tiny volatile char SCBR @0x19; /* SCI baud rate register */
/* INTERRUPT section
*/
@tiny volatile char INTKBSCR @0x1a; /* Keyboard control/status register */
@tiny volatile char INTKBIER @0x1b; /* Keyboard interrupt Enable register */
@tiny volatile char TBCR @0x1c; /* Time Base Module control register */
@tiny volatile char INTSCR @0x1d; /* IRQ control/status register */
/* OPTION section
*/
@tiny volatile char CONFIG2 @0x1e; /* Configuration register 2 */
@tiny volatile char CONFIG1 @0x1f; /*Configuration register 1 */
/* TIMER section
*/
@tiny volatile char T1SC @0x20; /* timer status/ctrl register */
@tiny volatile char T1CNTH @0x21; /* timer 1 Counter register high */
@tiny volatile char T1CNTL @0x22; /* timer 1 counter register low */
@tiny volatile char T1MODH @0x23; /* timer 1 counter modulo register high */
@tiny volatile char T1MODL @0x24; /* timer 1 counter modulo register low */
@tiny volatile char T1SC0 @0x25; /* timer 1 channel 0 status/ctrl register*/
@tiny volatile char T1CH0H @0x26; /* timer 1 channel 0 register high */
@tiny volatile char T1CH0L @0x27; /* timer 1 channel 0 register low */
@tiny volatile char T1SC1 @0x28; /* timer 1 channel 1 status/ctrl register */
@tiny volatile int T1CH1 @0x29; /* timer 1 channel 1 register */
@tiny volatile char T1CH1H @0x29; /* timer 1 channel 1 register high */
@tiny volatile char T1CH1L @0x2a; /* timer 1 channel 1 register low */
@tiny volatile char T2SC @0x2b; /* timer 2 status/ctrl regisger */
@tiny volatile char T2CNTH @0x2c; /* timer 2 counter register high */
@tiny volatile char T2CNTL @0x2d; /* timer 2 counter register low */
@tiny volatile char T2MODH @0x2e; /* timer 2 counter modelo register high */
@tiny volatile char T2MODL @0x2f; /* timer 2 counter modelo register low */
@tiny volatile char T2SC0 @0x30; /* timer 2 channel 0 status/ctrl register */
@tiny volatile char T2CH0H @0x31; /* timer 2 channel 0 register high */
@tiny volatile char T2CH0L @0x32; /* timer 2 channel 0 register low */
@tiny volatile char T2SC1 @0x33; /* timer 2 channel 1 status/ctrl register */
@tiny volatile char T2CH1H @0x34; /* timer 2 channel 1 register high */
@tiny volatile char T2CH1L @0x35; /* timer 2 channel 1 register low */
/* PLL section
*/
@tiny volatile char PCTL @0x36; /* pll control register */
@tiny volatile char PBWC @0x37; /* pll bandwidth control register */
@tiny volatile char PMSH @0x38; /* pll multiplier select high register */
@tiny volatile char PMSL @0x39; /* pll multiplier select low register */
@tiny volatile char PMRS @0x3a; /* pll VCO select range register */
@tiny volatile char PMDS @0x3b; /* pll reference divider select register */
/* analog to digital section
*/
@tiny volatile char ADSCR @0x3c; /* analog to digital status/Ctrl register */
@tiny volatile char ADR @0x3d; /* analog to digital data register*/
@tiny volatile char ADCLK @0x3e; /* analog to digital clock register */
/* SIM section
*/
@near volatile char SBSR @0xfe00; /* SIM break status register */
@near volatile char SRSR @0xfe01; /* SIM reset status register */
@near volatile char SUBAR @0xfe02; /* SIM upper byte address register */
@near volatile char SBFCR @0xfe03; /* SIM break control register */
@near volatile char INT1 @0xfe04; /* interrupt status register1 */
@near volatile char INT2 @0xfe05; /* interrupt status register2 */
@near volatile char INT3 @0xfe06; /* interrupt status register3 */
@near volatile char Reserved @0xfe07; /* */
@near volatile char FLCR @0xfe08; /* flash control register */
@near volatile char BRKH @0xfe09; /* BREAK address register high */
@near volatile char BRKL @0xfe0a; /* BREAK address register low */
@near volatile char BRKSCR @0xfe0b; /* BREAK status/ctrl register */
@near volatile char LVISR @0xfe0c; /* LVI status register */
@near volatile char FLBPR @0xfe0e; /* flash blook protect register */
@near volatile char COPCTL @0xffff; /* COP control register */
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