<!--
This XML file (created on Sun Jun 15 09:18:47 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>001b387d5bdc</host_id>
	<nic_id>001b77ced793</nic_id>
	<cdrive_id>2a1d0905</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_tan</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Sun Jun 15 09:18:48 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1662</cpu_freq>
	</cpu>
	<ram units="MB">504</ram>
</machine>
<project>D:/楊淼的畢業設計/bs/QAM</project>
<revision>QAM</revision>
<compilation_summary>
	<flow_status>Successful - Sun Jun 15 09:18:47 2008</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>QAM</revision_name>
	<top_level_entity_name>QAM</top_level_entity_name>
	<family>Cyclone II</family>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_logic_elements>128 / 4,608 ( 3 % )</total_logic_elements>
	<total_registers>33</total_registers>
	<total_pins>11 / 89 ( 12 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 119,808 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 26 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 2 ( 0 % )</total_plls>
	<device>EP2C5T144C6</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off QAM -c QAM --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<clock_settings_summary>
	<row>
		<clock_node_name>CNT_CLK</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>18.187 ns</actual>
	</nonclk>
	<clk>
		<name>CNT_CLK</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>Restricted to 420.17 MHz ( period = 2.380 ns )</actual>
	</clk>
</performance>
</talkback>