|ok
m => process0~0.IN0
clk => kongzhi:a1.clk
reset => b1_temp[2].ACLR
reset => b1_temp[1].ACLR
reset => b1_temp[0].ACLR
reset => b2_temp[3].PRESET
reset => b2_temp[2].PRESET
reset => b2_temp[1].PRESET
reset => b2_temp[0].PRESET
reset => count1[3].ACLR
reset => n[0].ACLR
reset => b1_temp[3].ACLR
reset => count1[2].ACLR
reset => count1[1].ACLR
reset => count1[0].ACLR
reset => count2[3].ACLR
reset => count2[2].ACLR
reset => count2[1].ACLR
reset => count2[0].ACLR
reset => kongzhi:a1.reset
reset => n[1].ACLR
a[0] => r~0.IN0
a[0] => b1_temp~3.DATAA
a[0] => b2_temp~4.IN0
a[0] => b1_temp~7.DATAA
a[0] => n~0.OUTPUTSELECT
a[0] => n~1.OUTPUTSELECT
a[0] => b1_temp~8.OUTPUTSELECT
a[0] => b1_temp~9.OUTPUTSELECT
a[0] => b1_temp~10.OUTPUTSELECT
a[0] => b1_temp~11.OUTPUTSELECT
a[0] => b2_temp~9.OUTPUTSELECT
a[0] => b2_temp~10.OUTPUTSELECT
a[0] => b2_temp~11.OUTPUTSELECT
a[0] => b2_temp~12.OUTPUTSELECT
a[0] => count1~8.OUTPUTSELECT
a[0] => count1~9.OUTPUTSELECT
a[0] => count1~10.OUTPUTSELECT
a[0] => count1~11.OUTPUTSELECT
a[1] => r~1.IN0
a[1] => reduce_nor~5.IN1
a[1] => b1_temp~2.DATAA
a[1] => equal~6.IN0
a[1] => b1_temp~6.DATAA
a[2] => r~2.IN0
a[2] => reduce_nor~4.IN1
a[2] => reduce_nor~5.IN0
a[2] => b1_temp~1.DATAA
a[2] => equal~4.IN0
a[2] => b1_temp~5.DATAA
a[3] => r~3.IN0
a[3] => reduce_nor~4.IN0
a[3] => b1_temp~0.DATAA
a[3] => equal~5.IN0
a[3] => b1_temp~4.DATAA
b1[0] <= b1_temp[0].DB_MAX_OUTPUT_PORT_TYPE
b1[1] <= b1_temp[1].DB_MAX_OUTPUT_PORT_TYPE
b1[2] <= b1_temp[2].DB_MAX_OUTPUT_PORT_TYPE
b1[3] <= b1_temp[3].DB_MAX_OUTPUT_PORT_TYPE
b2[0] <= b2_temp[0].DB_MAX_OUTPUT_PORT_TYPE
b2[1] <= b2_temp[1].DB_MAX_OUTPUT_PORT_TYPE
b2[2] <= b2_temp[2].DB_MAX_OUTPUT_PORT_TYPE
b2[3] <= b2_temp[3].DB_MAX_OUTPUT_PORT_TYPE
b[0] <= display:a2.b[0]
b[1] <= display:a2.b[1]
b[2] <= display:a2.b[2]
b[3] <= display:a2.b[3]
b[4] <= display:a2.b[4]
b[5] <= display:a2.b[5]
b[6] <= display:a2.b[6]
disp[0] <= kongzhi:a1.b[0]
disp[1] <= kongzhi:a1.b[1]
disp[2] <= kongzhi:a1.b[2]
disp[3] <= kongzhi:a1.b[3]
disp[4] <= kongzhi:a1.b[4]
disp[5] <= kongzhi:a1.b[5]
level[0] => ~NO_FANOUT~
level[1] => ~NO_FANOUT~
level[2] => ~NO_FANOUT~
level[3] => ~NO_FANOUT~


|ok|kongzhi:a1
clk => a[1]~reg0.CLK
clk => a[0]~reg0.CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => a[2]~reg0.CLK
reset => temp[4].PRESET
reset => temp[3].PRESET
reset => temp[2].PRESET
reset => temp[1].ACLR
reset => temp[0].ACLR
reset => a~13.OUTPUTSELECT
reset => a~14.OUTPUTSELECT
reset => a~15.OUTPUTSELECT
reset => temp[5].PRESET
a[0] <= a[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
a[1] <= a[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
a[2] <= a[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
b[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
b[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
b[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
b[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
b[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
b[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE


|ok|display:a2
n[0] => reduce_nor~0.IN1
n[0] => equal~0.IN0
n[1] => reduce_nor~0.IN0
n[1] => reduce_nor~1.IN0
b1_temp[0] => equal~1.IN0
b1_temp[1] => equal~2.IN0
b1_temp[2] => equal~3.IN0
b1_temp[3] => equal~4.IN0
a[0] => Mux~1.IN8
a[0] => Mux~2.IN8
a[0] => Mux~3.IN8
a[0] => Mux~4.IN8
a[0] => Mux~5.IN8
a[0] => Mux~6.IN8
a[0] => Mux~7.IN8
a[0] => Mux~8.IN8
a[0] => Mux~9.IN8
a[0] => Mux~10.IN8
a[0] => Mux~11.IN8
a[0] => Mux~12.IN8
a[0] => Mux~13.IN8
a[0] => Mux~14.IN8
a[0] => Mux~15.IN8
a[0] => Mux~16.IN8
a[0] => Mux~17.IN8
a[0] => Mux~18.IN8
a[0] => Mux~19.IN8
a[0] => Mux~20.IN8
a[0] => Mux~21.IN8
a[1] => Mux~0.IN5
a[1] => Mux~1.IN7
a[1] => Mux~2.IN7
a[1] => Mux~3.IN7
a[1] => Mux~4.IN7
a[1] => Mux~5.IN7
a[1] => Mux~6.IN7
a[1] => Mux~7.IN7
a[1] => Mux~8.IN7
a[1] => Mux~9.IN7
a[1] => Mux~10.IN7
a[1] => Mux~11.IN7
a[1] => Mux~12.IN7
a[1] => Mux~13.IN7
a[1] => Mux~14.IN7
a[1] => Mux~15.IN7
a[1] => Mux~16.IN7
a[1] => Mux~17.IN7
a[1] => Mux~18.IN7
a[1] => Mux~19.IN7
a[1] => Mux~20.IN7
a[1] => Mux~21.IN7
a[2] => Mux~0.IN4
a[2] => Mux~1.IN6
a[2] => Mux~2.IN6
a[2] => Mux~3.IN6
a[2] => Mux~4.IN6
a[2] => Mux~5.IN6
a[2] => Mux~6.IN6
a[2] => Mux~7.IN6
a[2] => Mux~8.IN6
a[2] => Mux~9.IN6
a[2] => Mux~10.IN6
a[2] => Mux~11.IN6
a[2] => Mux~12.IN6
a[2] => Mux~13.IN6
a[2] => Mux~14.IN6
a[2] => Mux~15.IN6
a[2] => Mux~16.IN6
a[2] => Mux~17.IN6
a[2] => Mux~18.IN6
a[2] => Mux~19.IN6
a[2] => Mux~20.IN6
a[2] => Mux~21.IN6
b[0] <= b~20.DB_MAX_OUTPUT_PORT_TYPE
b[1] <= b~19.DB_MAX_OUTPUT_PORT_TYPE
b[2] <= b~18.DB_MAX_OUTPUT_PORT_TYPE
b[3] <= b~17.DB_MAX_OUTPUT_PORT_TYPE
b[4] <= b~16.DB_MAX_OUTPUT_PORT_TYPE
b[5] <= b~15.DB_MAX_OUTPUT_PORT_TYPE
b[6] <= b~14.DB_MAX_OUTPUT_PORT_TYPE
u[0] => Mux~7.IN9
u[0] => Mux~14.IN9
u[0] => Mux~21.IN9
u[1] => Mux~6.IN9
u[1] => Mux~13.IN9
u[1] => Mux~20.IN9
u[2] => Mux~5.IN9
u[2] => Mux~12.IN9
u[2] => Mux~19.IN9
u[3] => Mux~4.IN9
u[3] => Mux~11.IN9
u[3] => Mux~18.IN9
u[4] => Mux~3.IN9
u[4] => Mux~10.IN9
u[4] => Mux~17.IN9
u[5] => Mux~2.IN9
u[5] => Mux~9.IN9
u[5] => Mux~16.IN9
u[6] => Mux~1.IN9
u[6] => Mux~8.IN9
u[6] => Mux~15.IN9
v[0] => Mux~7.IN10
v[0] => Mux~14.IN10
v[0] => Mux~21.IN10
v[1] => Mux~6.IN10
v[1] => Mux~13.IN10
v[1] => Mux~20.IN10
v[2] => Mux~5.IN10
v[2] => Mux~12.IN10
v[2] => Mux~19.IN10
v[3] => Mux~4.IN10
v[3] => Mux~11.IN10
v[3] => Mux~18.IN10
v[4] => Mux~3.IN10
v[4] => Mux~10.IN10
v[4] => Mux~17.IN10
v[5] => Mux~2.IN10
v[5] => Mux~9.IN10
v[5] => Mux~16.IN10
v[6] => Mux~1.IN10
v[6] => Mux~8.IN10
v[6] => Mux~15.IN10