{ "Info" "ITDB_TH_RESULT" "b1_temp\[2\] a\[0\] m 4.000 ns register " "Info: th for register b1_temp\[2\] (data pin = a\[0\], clock pin = m) is 4.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m destination 10.000 ns + Longest register " "Info: + Longest clock path from clock m to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns m 1 CLK PIN_4 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 14; CLK Node = 'm'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { m } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns b1_temp\[2\] 2 REG LC35 110 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 110; REG Node = 'b1_temp\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { m b1_temp[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m b1_temp[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a\[0\] 1 PIN PIN_57 123 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_57; Fanout = 123; PIN Node = 'a\[0\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { a[0] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns b1_temp\[2\] 2 REG LC35 110 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 110; REG Node = 'b1_temp\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { a[0] b1_temp[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { a[0] b1_temp[2] } "NODE_NAME" } } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m b1_temp[2] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { a[0] b1_temp[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk disp\[3\] kongzhi:a1\|temp\[3\] 8.000 ns register " "Info: Minimum tco from clock clk to destination pin disp\[3\] through register kongzhi:a1\|temp\[3\] is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 9 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns kongzhi:a1\|temp\[3\] 2 REG LC56 18 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'kongzhi:a1\|temp\[3\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "0.000 ns" { clk kongzhi:a1|temp[3] } "NODE_NAME" } } } { "D:/0510719/復件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/復件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/0510719/復件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/復件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kongzhi:a1\|temp\[3\] 1 REG LC56 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'kongzhi:a1\|temp\[3\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { kongzhi:a1|temp[3] } "NODE_NAME" } } } { "D:/0510719/復件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/復件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns disp\[3\] 2 PIN PIN_37 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'disp\[3\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "4.000 ns" { kongzhi:a1|temp[3] disp[3] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "4.000 ns" { kongzhi:a1|temp[3] disp[3] } "NODE_NAME" } } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[3] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "4.000 ns" { kongzhi:a1|temp[3] disp[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 31 14:26:49 2002 " "Info: Processing ended: Thu Jan 31 14:26:49 2002" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}