library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kongzhi is
  port(
    clk:in std_logic;
    reset:std_logic;
    a:out std_logic_vector(2 downto 0);
    b:out std_logic_vector(5 downto 0)
  );
end;
architecture kk of kongzhi is
signal temp:std_logic_vector(5 downto 0);
begin
  process(clk,reset,temp)			
  begin
  if(reset='1')then					--復位
    temp<="111100";
  else
    if(clk'event and clk='1')then	
	  if(temp="111110")then
        a<="000";
        temp<="011111";
      elsif(temp="011111")then
        a<="001";
        temp<="101111";
      elsif(temp="101111")then
        a<="010";
        temp<="110111";
      elsif(temp="110111")then
        a<="011";
        temp<="111011";
      elsif(temp="111011")then
        a<="100";
        temp<="111101";
      elsif(temp="111101")then
        a<="101";
        temp<="111110";
      else
        a<="000";
        temp<="011111";
      end if;
    end if;
  end if;
b<=temp;
end process;
end;