///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : alpha_buf.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : yuan.liuqing@zte.com.cn
///
/// Module_name  : alpha_buf
/// Called by    : max_log_map  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// alpha_buf-----|----alpha_ram
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-17  | 建立文件
/// 1.0-1       | 2007-12-21  | 修改格式，fang.yongzhong
///---------------------------------------------------------------------
// Main Function:
/// 1、CTC譯碼核alpha計算數(shù)據(jù)緩存
///*********************************************************************

`timescale 1ns/100ps

module alpha_buf
    #(parameter WIN_SIZE            = 6'd32,        ///sliding window size, unit: lattice
                STATE_MATRIC_WIDTH  = 6'd12,        ///狀態(tài)度量數(shù)據(jù)寬度
                ALPHA_RAM_ADR_WIDTH = 6'd7          ///alpha_buf地址寬度
                 )
    (
    ///system i/f
    input              clk_sys,                     ///系統(tǒng)時鐘信號
    input              rst_b,                       ///輸入復(fù)位信號
    ///input i/f
    input       [STATE_MATRIC_WIDTH*8-1:0]    alpha,
    input                                     alpha_source_val,     ///輸入使能信號
    input                                     clr_alpha_buf,        ///清空buf信號
    ///output i/f
    output wire [STATE_MATRIC_WIDTH*8-1:0]    alpha_buf_out,
    input                                     rd_alpha_buf
    );

///*********************************************************************
///內(nèi)部信號定義
///*********************************************************************
reg     [ALPHA_RAM_ADR_WIDTH-1:0]   forward_adr;    ///incremental adr for wr/rd circular_buffer_cell
reg     [ALPHA_RAM_ADR_WIDTH-1:0]   backward_adr;   ///decreasing adr for rd circular_buffer_cell

///*************************************************************************
///Notes:
///alpha_buf has a ping-pong structure, ping-ram and pong-ram distinguish themselves
///by different address space in a dpram.
///Input data has a incremental wr address, namely from 0 to WIN_SIZE-1 in ping/pong ram.
///Output data has a decreasing rd address, namely from WIN_SIZE-1 to 0 in ping/pong ram.
///*************************************************************************

///generate forward_adr according to WIN_SIZE parameter
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        forward_adr <= 1'b0;
    else if( clr_alpha_buf )
        forward_adr <= 1'b0;
    else if( alpha_source_val )
        begin
        if( forward_adr==(WIN_SIZE-1'b1) )
            forward_adr <= 7'd64;
        else if( forward_adr==(7'd64+WIN_SIZE-1'b1) )
            forward_adr <= 1'b0;
        else
            forward_adr <= forward_adr + 1'b1;
        end
    else
        forward_adr <= forward_adr;
end

///generate backward_adr according to WIN_SIZE parameter
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        backward_adr <= WIN_SIZE-1'b1;
    else if( clr_alpha_buf )
        backward_adr <= WIN_SIZE-1'b1;
    else if( rd_alpha_buf )
        begin
        if( backward_adr==1'b0 )
            backward_adr <= 7'd64+WIN_SIZE-1'b1;
        else if( backward_adr==7'd64  )
            backward_adr <= WIN_SIZE-1'b1;
        else
            backward_adr <= backward_adr - 1'b1;
        end

    else
        backward_adr <= backward_adr;
end

///instantiate alpha_ram
///dpram parameters: 96-b x 128, no output register, singal clock, wr_port_width=rd_port_width
alpha_ram alpha_ram
(
    .clock     (clk_sys         ),
    .data      (alpha           ),
    .rdaddress (backward_adr    ),
    .rden      (rd_alpha_buf    ),
    .wraddress (forward_adr     ),
    .wren      (alpha_source_val),
    .q         (alpha_buf_out   )
);

endmodule ///alpha_buf