///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_path_top.v
/// Author       : wangjinshan
/// Department   : 2nd IC department
/// Email        : wang.jinshan1@zte.com.cn
///
/// Module_name  : ctc_path_top
/// Called by    : fec_decoder_top  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///                  |----pre_ctc_fifo
/// ctc_path_top-----|----ctc_decoder
///                  |----post_ctc_fifo
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-16  | 建立文件
///---------------------------------------------------------------------
// Main Function:
/// 1、CTC譯碼器頂層文件
///*********************************************************************

`timescale 1ns / 100ps

module ctc_path_top
(
    ///system signals
    input              sys_clk,                     ///系統時鐘信號
    input              ctc_clk,                     ///CTC譯碼器時鐘信號
    input              clk_rd_post_ctc_fifo,        ///post_ctc_fifo讀時鐘
    input              rst_b,                       ///復位信號
    ///pre_proc wr i/f
    output wire        full,                        ///數據輸入FIFO滿信號
    input              wr,                          ///數據輸入FIFO寫信號
    input              eop_wr,                      ///數據輸入FIFO寫結束信號
    input       [31:0] dat_wr,                      ///數據輸入FIFO數據信號線
    ///fec_mux rd i/f
    output wire        empty,                       ///數據輸出FIFO空信號
    input              rd,                          ///數據輸出FIFO讀信號
    output wire        eop_rd,                      ///數據輸出FIFO讀結束信號
    output wire [31:0] dat_rd                       ///數據輸出FIFO數據信號線
);

///*********************************************************************
///內部信號定義
///*********************************************************************
wire             empty_pre_ctc_fifo;                ///數據輸入FIFO空信號
wire     [12:0]  usedw_pre_ctc_fifo;                ///數據輸入FIFO空間使用
wire             rd_pre_ctc_fifo;                   ///數據輸入FIFO讀信號
wire             eop_rd_pre_ctc_fifo;               ///數據輸入FIFO結束信號
wire     [31:0]  dat_rd_pre_ctc_fifo;               ///數據輸入FIFO數據線

wire             full_post_ctc_fifo;                ///數據輸出FIFO滿信號
wire             wr_post_ctc_fifo;                  ///數據輸出FIFO寫信號
wire             eop_wr_post_ctc_fifo;              ///數據輸出FIFO寫結束信號
wire     [31:0]  dat_wr_post_ctc_fifo;              ///數據輸出FIFO數據線
wire     [8:0]   wrusedw_post_ctc_fifo;             ///數據輸出FIFO空間使用

pre_ctc_fifo    pre_ctc_fifo
(
    //system signals
    .wr_clk         (sys_clk                  ),
    .rd_clk         (ctc_clk                  ),
    .rst_b          (rst_b                    ),
    //pre_proc wr i/f
    .full           (full                     ),
    .wr             (wr                       ),
    .eop_wr         (eop_wr                   ),
    .dat_wr         (dat_wr[31:0]             ),
    //ctc_decoder rd i/f
    .empty          (empty_pre_ctc_fifo       ),
    .usedw          (usedw_pre_ctc_fifo       ),
    .rd             (rd_pre_ctc_fifo          ),
    .eop_rd         (eop_rd_pre_ctc_fifo      ),
    .dat_rd         (dat_rd_pre_ctc_fifo[31:0])
);

ctc_decoder ctc_decoder
(
    .sys_clk                    (ctc_clk              ),
    .reset_b                    (rst_b                ),
    .empty_pre_ctc_fifo         (empty_pre_ctc_fifo   ),
    .usedw_pre_ctc_fifo         (usedw_pre_ctc_fifo   ),
    .rd_pre_ctc_fifo            (rd_pre_ctc_fifo      ),
    .eop_rd_pre_ctc_fifo        (eop_rd_pre_ctc_fifo  ),
    .dat_rd_pre_ctc_fifo        (dat_rd_pre_ctc_fifo  ),
    .full_post_ctc_fifo         (full_post_ctc_fifo   ),
    .empty_post_ctc_fifo        (empty                ),
    .wr_post_ctc_fifo           (wr_post_ctc_fifo     ),
    .eop_wr_post_ctc_fifo       (eop_wr_post_ctc_fifo ),
    .dat_wr_post_ctc_fifo       (dat_wr_post_ctc_fifo ),
    .wrusedword_post_ctc_fifo   (wrusedw_post_ctc_fifo)
);

post_ctc_fifo   post_ctc_fifo
(
    //system signals
    .clk_wr_fifo    (ctc_clk                   ),
    .clk_rd_fifo    (clk_rd_post_ctc_fifo      ),
    .rst_b          (rst_b                     ),
    //ctc_decoder wr i/f
    .full           (full_post_ctc_fifo        ),
    .wr             (wr_post_ctc_fifo          ),
    .eop_wr         (eop_wr_post_ctc_fifo      ),
    .dat_wr         (dat_wr_post_ctc_fifo[31:0]),
    .wrusedw        (wrusedw_post_ctc_fifo[8:0]),
    //fec_mux rd i/f
    .empty          (empty                     ),
    .rd             (rd                        ),
    .eop_rd         (eop_rd                    ),
    .dat_rd         (dat_rd[31:0]              )
);

endmodule ///ctc_path_top