///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : sliding_win_fsm.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : yuan.liuqing@zte.com.cn
///
/// Module_name  : sliding_win_fsm
/// Called by    : max_log_map  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// none
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-17  | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC譯碼核滑動窗調(diào)度模塊
///*********************************************************************

`timescale 1ns/100ps
  
module sliding_win_fsm
    #(parameter WIN_SIZE            = 6'd32     )   ///sliding window size, unit: lattice
    (
    ///system i/f
    input              clk_sys,                     ///系統(tǒng)時鐘信號
    input              rst_b,                       ///輸入復(fù)位信號
    ///input i/f
    input              sop_source,
    input              eop_source,
    input              val_source,
    input              alpha_sink_val,
    input              beta_sink_val0,
    input              beta_sink_val1,
    input       [15:0] packet_length,               ///包長
    ///output i/f
    output wire        clr_cal_buf,                 ///清除buf信號
    output reg  [1:0]  beta_sel,                    ///beta計算單元選擇信號
    output reg         new_beta_cal0,               ///beta1計算單元復(fù)位信號
    output reg         new_beta_cal1,               ///beta2計算單元復(fù)位信號
    output reg         rd_cir_buf_cell0,
    output reg         rd_cir_buf_cell1,
    output reg         rd_cir_buf_cell2,
    output wire        wr_alpha_buf,                ///alpha_buf 寫信號
    output wire        rd_alpha_buf,                ///alpha_buf 讀信號
    output reg         sop_sink,
    output reg         eop_sink
    );

///*********************************************************************
///內(nèi)部信號定義
///*********************************************************************
    reg     [11:0]          block_cir_buf_wr_counter;
    reg     [7:0]           eop_source_pass_counter;
    reg     [7:0]           cir_buf_wr_win_counter;
    reg                     pre_win_parity_flag;
    wire                    win_parity_flag;
    reg                     eop_flag;
 ///*********************************************************************
///主程序代碼：
///*********************************************************************
                           
    assign                  clr_cal_buf = eop_sink;
    
    //*************************************************************************
    //counter: 
    //  block_cir_buf_wr_counter, 
    //  cir_buf_wr_win_counter,
    //  eop_source_pass_counter
    //*************************************************************************
    
    //block_cir_buf_wr_counter
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                block_cir_buf_wr_counter <= 12'd0;
            else 
                begin
                    if( clr_cal_buf )
                        block_cir_buf_wr_counter <= 12'd0;
                    else if( sop_source || block_cir_buf_wr_counter!==12'd0 )
                        block_cir_buf_wr_counter <= block_cir_buf_wr_counter + 12'd1;
                    else
                        block_cir_buf_wr_counter <= block_cir_buf_wr_counter;
                end
        end

    //generate win_parity_flag
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    cir_buf_wr_win_counter <= 8'b0;
                    pre_win_parity_flag <= 1'b0;
                end
            else 
                begin
                    if( clr_cal_buf )
                        begin
                            cir_buf_wr_win_counter <= 8'b0;
                            pre_win_parity_flag <= 1'b0;
                        end
                    else if( val_source )//sop_source || block_cir_buf_wr_counter!==12'd0
                        begin
                            if( cir_buf_wr_win_counter==(WIN_SIZE-1'b1) )
                                begin
                                    cir_buf_wr_win_counter <= 8'b0;
                                    pre_win_parity_flag <= ~pre_win_parity_flag;
                                end
                            else
                                begin
                                    cir_buf_wr_win_counter <= cir_buf_wr_win_counter + 8'b1;
                                    pre_win_parity_flag <= pre_win_parity_flag;
                                end                              
                        end
                    else
                        begin
                            cir_buf_wr_win_counter <= 8'b0;
                            pre_win_parity_flag <= pre_win_parity_flag;
                        end               
                end
        end
 ///eliminate win_parity_flag glitch   
    assign win_parity_flag = pre_win_parity_flag;

    //eop_source_pass_counter
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    eop_source_pass_counter <= 8'b0;
                    eop_flag <= 1'b0;
                end
            else
                begin
                    if( clr_cal_buf )
                        begin
                            eop_source_pass_counter <= 8'b0;
                            eop_flag <= 1'b0;
                        end
                    else if( eop_source )
                        begin
                            eop_source_pass_counter <= 8'b1;
                            eop_flag <= 1'b1;
                        end
                    else
                        begin
                            if( eop_flag )
                                eop_source_pass_counter <= eop_source_pass_counter + 8'b1;
                            else
                                eop_source_pass_counter <= eop_source_pass_counter;
                            eop_flag <= eop_flag;
                        end
                end
        end

        
    //*************************************************************************
    //sop_sink,eop_sink
    //*************************************************************************
    
    //generate sop_sink
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    sop_sink <= 1'b0;                     
                end
            else 
                begin
                    if( block_cir_buf_wr_counter == (WIN_SIZE*4+4'd11) )  //fyz
                        begin
                            sop_sink <= 1'b1; 
                        end
                    else
                        begin
                            sop_sink <= 1'b0; 
                        end
                end
        end

    //genetate eop_sink
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    eop_sink <= 1'b0;                     
                end
            else 
                begin
                    if( eop_source_pass_counter == (WIN_SIZE*2+4'd11) )  //fyz
                        begin
                            eop_sink <= 1'b1; 
                        end
                    else
                        begin
                            eop_sink <= 1'b0; 
                        end
                end
        end        
    
       
    //*************************************************************************
    //generate alpha_buf rd/wr
    //*************************************************************************
    
    reg [7:0] alpha_val_counter;
    reg alpha_wr_en;
    reg [WIN_SIZE-1'b1:0] wr_alpha_buf_delay_line;

    assign wr_alpha_buf = alpha_sink_val && alpha_wr_en;
    assign rd_alpha_buf = wr_alpha_buf_delay_line[WIN_SIZE-1'b1];
            
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    alpha_val_counter <= 1'b0;                
                end
            else 
                begin
                    if( clr_cal_buf )
                        alpha_val_counter <= 1'b0;
                    else if( alpha_sink_val )
                        begin
                            if( alpha_val_counter==(WIN_SIZE-1'b1) )
                                alpha_val_counter <= 1'b0;
                            else
                                alpha_val_counter <= alpha_val_counter + 1'b1;                        
                        end
                    else
                        alpha_val_counter <= alpha_val_counter;
                end
        end

    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    alpha_wr_en <= 1'b0;                
                end
            else 
                begin
                    if( clr_cal_buf )
                        alpha_wr_en <= 1'b0;
                    else if( alpha_val_counter==(WIN_SIZE-2'd2) )
                        alpha_wr_en <= 1'b1;
                    else
                        alpha_wr_en <= alpha_wr_en;
                end
        end

    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                wr_alpha_buf_delay_line <= 1'b0;                
            else