;******************************************************************************
;               		SJTU DSP Tech. Center
;        Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
;  History:
;		Date		Authors			Changes
;		2003/08/30	Fu Xuan			Created.
;******************************************************************************
	.mmregs

FC_SET			.set 	0x0008
FC_CLR			.set 	0x0000

	.def		codec_init
	
	.include 	"codec_cnst.h54"
	.include 	"dsp_cnst.h54"
	.include 	"macro.h54"

	.text

;******************************************************************************
;** Function:	codec_init
;** Description:	Initialization for TLC320AD50C
;******************************************************************************
codec_init:
	ssbx	INTM						;disable interrupts
	
	stm		#FC_SET, AR2
	stm		#FC_CLR, AR3
	
	stm		#SPCR2, SPSA1				;SPCR21
	stm		#0x0101, SPSD1				;XRST=1, enable transmit, soft mode

;*************************************************************************
;				Data Format in Secondary Communication
;   D15 D14 D13 |D12 D11 D10 D9 D8| D7 D6 D5 D4 D3 D2 D1 D0
;            |  |     register    |   register
;           R/W |     address     |     data
;*************************************************************************
	ld      #0, A
	
	call 	wait_rdy				;wait until McBSP1 transmit complete
	stlm	A, DXR11
	nop
		
	portw   *(AR2), CNTL2			;set FC=1, 2nd communication request
	nop
	
	call 	wait_rdy
	stm     #(REG1_ADDR | REG1_SW_RESET | REG1_DAC_16MODE), DXR11	
									;REG1, Reset codec (D7), 16 bits DA
	call    wait_rdy
	stlm	A, DXR11				;write nop register
	nop
	
	portw 	*(AR3), CNTL2			;clear FC to 0
	
	stm		#4000, AR5
wait_reset:							;wait for codec to reset, clear out initial data
	nop
	banz	wait_reset, *AR5-

	call 	wait_rdy
	stlm	A, DXR11				;write nop register
	nop
		
	portw 	*(AR2), CNTL2
	nop

	;set control register 1	
	call 	wait_rdy
	stm		#(REG1_ADDR | REG1_DAC_16MODE), DXR11	
									;D/A16位精度
	
	;set control register 2
	call 	wait_rdy
	stm		#(REG2_ADDR | REG2_ADC_16MODE  | REG2_AL_DISABLE), DXR11	
									;A/D16位精度, 無模擬環(huán)路

	;set control register 3
	call 	wait_rdy
	stm		#REG3_ADDR, DXR11		;FS到FSD之間SCLK=0

	;set control register 4
	call 	wait_rdy
	;MCLK = 8.192 MHz, Fs=16kHz
	stm		#(REG4_ADDR | REG4_AIG_12DB | REG4_AOG_0DB | REG4_N_4 | REG4_DPLL_ENABLE), DXR11
	;模擬輸入12dB增益, 模擬輸出0dB, 采樣率N=4, PLL使能
	
	call 	wait_rdy
	stlm	A, DXR11				;write nop register
	nop
	
	portw	*(AR3), CNTL2			;clear FC to 0

	nop
	nop
	nop

	McBSP1_DISABLE	AR4				;disable McBSP1
	
	ret
	
;******************************************************************************
;** Function:	wait_rdy
;** Description:	wait for codec send int and clear FC
;******************************************************************************
wait_rdy:
	stm		#SPCR2, SPSA1
	bitf	*(SPSD1), #0x0002
	bc		wait_rdy, NTC
	
	ret
;end of codec_init.s54