?? dsp_init.s54
字號:
;******************************************************************************
; SJTU DSP Tech. Center
; Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
; History:
; Date Authors Changes
; 2003/08/30 Fu Xuan Created.
; 2007/09/23 Chen Yu Changed.
;******************************************************************************
.mmregs
.def DSPInit
.ref codec_init
.ref DATA_STORE_SIZE
.ref INPUT_PINGPONG_0
.ref INPUT_PINGPONG_1
.ref OUTPUT_PINGPONG_0
.ref OUTPUT_PINGPONG_1
.include "dsp_cnst.h54"
.include "codec_cnst.h54"
.include "macro.h54"
.text
;******************************************************************************
;** Function: DSPInit()
;** Description: DSP initialization
;******************************************************************************
DSPInit:
;set register ST1 to initialize DSP
; bit: 15 14 13 12 11 10 9 8 7 6 5 4-0
; | BRAF | CPL | XF | HM | INTM | 0 | OVM | SXM | C16 | FRCT | CMPT | ASM |
; x 1 x x 1 0 1 0 0 1 0 xxxxx
ssbx INTM ;close interrupt first
ssbx CPL ;use SP for direct addressing
rsbx SXM ;zero extended
rsbx C16 ;ALU run at double mode
rsbx CMPT ;standard mode
ssbx FRCT ;fraction mode
ssbx OVM ;result saturated to 32 bits
;set register PMST
; bit: 15-7 6 5 4 3 2 1 0
; | IPTR | MP/MC | OVLY | AVIS | DROM | CLKOFF | SMUL | SST |
; xxxx 1 1 0 x x 0 0
; PMST (IPTR=0x1, /MC=1, OVLY=1, SMUL=0, SST=0)
stm #0x00E0, PMST
;set register SWWSR
stm #0x7000, SWWSR
;let 3 LEDs shine for a while, then shut
LEDS_CHECK USER_REG
;-------------- McBSP 2------------------------
;disable McBSP before initialization
McBSP2_DISABLE AR3
;initialize registers
stm #MCBSP2_CNST, AR2
stm #SPSA2, AR3
stm #(15-1), BRC
rptb MCBSP2_loop-1
ld *AR2+, A
stl A, *AR3+
ld *AR2+, A
stl A, *AR3-
MCBSP2_loop:
;-------------- DMA ---------------------------
;set DMA0, DMA4 high priority, 中斷復(fù)用INTOSEL=10b(DMA1,2,3), close all other DMA
stm #0x5180, DMPREC ;AUTOIX=1, all DMA channels use its own reload registers
;DPRC[4,0]=11, set DMA0, DMA4 to high priority
;INTOSEL=10, use DMA1,2,3 interrupt
stm #DMA_CNST, AR3
stm #0, DMSA
stm #DMSDI, AR2
rpt #62-1
mvdd *AR3+, *AR2
;--------------Board Setting ------------------
;select codec as McBSP2 signal resource
ld #0x0, A
portw *(AL), MISC ;MISC=0x0000
portw *(AL), CODEC_CLK ;CODEC_CLK=0x0000
;codec initialization
call codec_init
ret
;end of DSPInit
;============================================================
.sect "DSPIni_table"
;******************************************************************************
; McBSP2 Init Constants
;******************************************************************************
MCBSP2_CNST:
.word 0 ;sub address==SPCR12
.word 0x0000 ;SPCR12
;DLB=0, disable digital loop
;RJUST=00, right justified, zero extended in DRR[1,2]
;CLKSTP=00, disable clock stop mode
;DXENA=0, close DX enable
;ABIS=0, disable A-bis mode
;RINTM=00, RINT driven by RRDY
;RSYNCERR=0, no error in received frame sync signal
;RFULL=0, RBR[1,2] are not full
;RRDY, receiving is not ready
;/RRST=0, reset the receiving
.word 1 ;sub address==SPCR22
.word 0x0100 ;SPCR22
;FREE=0, disable free run mode
;SOFT=1, enable SOFT mode
;/FRST=0, reset the frame sync signal generator
;/GRST=0, reset the sample rate generator
;XINTM=00, XINT driven by XRDY
;XSYNCERR=0, no error in transmitted frame sync signal
;/XEMPTY=0, XSR[1,2] are not empty
;XRDY=0, transmition is not ready
;/XRST=0, reset the transmition
.word 2 ;sub address==RCR12
.word 0x0140 ;RCR12
;RFRLEN1=0000001, 2 words per frame
;RWDLEN1=010, 16 bits per word
.word 3 ;sub address==RCR22
.word 0x0000 ;RCR22
;RPHASE=0, single-phase frame
;RFRLEN2=0000000, ignored
;RWDLEN2=000, ignored
;RCOMPAND=00, no expandition, MSB first
;RFIG=0, frame synchronized in each receiving
;RDATDLY=00, 0 bit delay
.word 4 ;sub address==XCR12
.word 0x0140 ;XCR12
;XFRLEN1=0000001, 2 words per frame
;XWDLEN1=010, 16 bits per word
.word 5 ;sub address==XCR22
.word 0x0000 ;XCR22
;XPHASE=0, single-phase frame
;XFRLEN2, XWDLEN2 are ignored
;XCOMPAND=00, no expandition, MSB first
;XFIG=0, frame synchronized in each transmition
;XDATDLY=00, 0 bit delay
.word 6 ;sub address==SRGR12
.word 0 ;SRGR12
.word 7 ;sub address==SRGR22
.word 0 ;SRGR22
.word 8 ;sub address==MCR12
.word 0 ;MCR12
;RMCM=0, enable all 128 channels
.word 9 ;sub address==MCR22
.word 0 ;MCR22
;XMCM=00, enable all 128 channels
.word 10 ;sub address==RCERA2
.word 0 ;RCERA2
.word 11 ;sub address==RCERB2
.word 0 ;RCERB2
.word 12 ;sub address==XCERA2
.word 0 ;XCERA2
.word 13 ;sub address==XCERB2
.word 0 ;XCERB2
.word 14 ;sub address==PCR1
.word 0x0003 ;XIOEN=RIOEN=0, DX, FSX, CLKX, DR, FSR, CLKR, CLKS are used for McBSP
;FSXM=FSRM=0, external driven
;CLKXM=CLKRM=0, external driven
;FSXP=FSRP=0, high-valid frame sync impulse
;CLKXP=1, transmit data sampled on the falling edge of CLKX
;CLKRP=1, receive data sampled on the rising edge of CLKR
;******************************************************************************
; DMA Init Constants
;******************************************************************************
DMA_CNST:
.word DRR12 ;DMSRC0, McBSP2 receive register
.word INPUT_PINGPONG_0 ;DMDST0
.word DATA_STORE_SIZE-1 ;DMCTR0, (number of elements)-1
.word 0x3000 ;DMSFC0
;DSYN=0011b, McBSP2 receive event
;DBLW=0, single word mode
;FRMCNT=0, one frame transferred each time
.word 0xE045 ;DMMCR0
;AUTOINIT=1, enable auto-initializtion
;DINM=1, generate interrupt according to IMOD
;IMOD=1, generate interrupt at the end of one frame or one block
;CTMOD=0, multi-frame mode
;SIND=000, source address is not modified
;DMS=01, source address is in data space
;DIND=001, destination address is modifed by post-add 1
;DMD=01, destination address is in data space
.word 0 ;DMSRC1
.word 0 ;DMDST1
.word 0 ;DMCTR1
.word 0 ;DMSFC1
.word 0 ;DMMCR1
.word 0 ;DMSRC2
.word 0 ;DMDST2
.word 0 ;DMCTR2
.word 0 ;DMSFC2
.word 0 ;DMMCR2
.word 0 ;DMSRC3
.word 0 ;DMDST3
.word 0 ;DMCTR3
.word 0 ;DMSFC3
.word 0 ;DMMCR3
.word OUTPUT_PINGPONG_0 ;DMSRC4
.word DXR12 ;DMDST4, McBSP2 transmit register
.word DATA_STORE_SIZE-1 ;DMCTR4, (number of elements)-1
.word 0x4000 ;DMSFC4
;DSYN=0100b, McBSP2 transmit event
;DBLW=0, single word mode
;FRMCNT=0, one frame transferred each time
.word 0xE141 ;DMMCR4
;AUTOINIT=1, enable auto-initialization
;DINM=1, generate interrupt according to IMOD
;IMOD=1, generate interrupt at the end of one frame or one block
;CTMOD=0, multi-frame mode
;SIND=001, source address is modified by post-add 1
;DMS=01, source address is in data space
;DIND=000, destination address is not modified
;DMD=01, destination address is in data space
.word 0 ;DMSRC5
.word 0 ;DMDST5
.word 0 ;DMCTR5
.word 0 ;DMSFC5
.word 0 ;DMMCR5
.word 0 ;DMSRCP, no extended addressing
.word 0 ;DMDSTP, no extended addressing
.word 0 ;DMIDX0
.word 0 ;DMIDX1
.word 0 ;DMFRI0
.word 0 ;DMFRI1
.word DRR12 ;DMGSA0, global source address reload register
.word INPUT_PINGPONG_1 ;DMGDA0, global destination address reload register
.word DATA_STORE_SIZE-1 ;DMGCR0, global element count reload register
.word 0 ;DMGFR0, global frame count reload register
.word 0 ;XSRCDP
.word 0 ;XDSTDP
.word 0 ;DMGSA1
.word 0 ;DMGDA1
.word 0 ;DMGCR1
.word 0 ;DMGFR1
.word 0 ;DMGSA2
.word 0 ;DMGDA2
.word 0 ;DMGCR2
.word 0 ;DMGFR2
.word 0 ;DMGSA3
.word 0 ;DMGDA3
.word 0 ;DMGCR3
.word 0 ;DMGFR3
.word OUTPUT_PINGPONG_1 ;DMGSA4
.word DXR12 ;DMGDA4
.word DATA_STORE_SIZE-1 ;DMGCR4
.word 0 ;DMGFR4
.word 0 ;DMGSA5
.word 0 ;DMGDA5
.word 0 ;DMGCR5
.word 0 ;DMGFR5
;end of dsp_init.s54?? 快捷鍵說明
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