;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Hclk / 8
;//     <o7.18..19>  PCLK_UART3: Peripheral Clock Selection for UART3
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Hclk / 8
;//     <o7.20..21>   PCLK_I2C2: Peripheral Clock Selection for I2C2
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Hclk / 8
;//     <o7.22..23>    PCLK_I2S: Peripheral Clock Selection for I2S
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Hclk / 8
;//     <o7.24..25>    PCLK_MCI: Peripheral Clock Selection for MCI
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Hclk / 8
;//     <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
;//                     <0=> Pclk = Cclk / 4
;//                     <1=> Pclk = Cclk
;//                     <2=> Pclk = Cclk / 2
;//                     <3=> Pclk = Hclk / 8
;//   </h>
;//   <h> Power Control for Peripherals Register (PCONP)
;//     <o8.31>     PCUSB: USB interface power/clock enable
;//     <o8.30>     PCENET: Ethernet block power/clock enable
;//     <o8.29>     PCGPDMA: GP DMA function power/clock enable
;//     <o8.28>     PCSDC: SD card interface power/clock enable
;//     <o8.27>     PCI2S: I2S interface power/clock enable
;//     <o8.26>     PCI2C2: I2C interface 2 power/clock enable
;//     <o8.25>     PCUART3: UART 3 power/clock enable
;//     <o8.24>     PCUART2: UART 2 power/clock enable
;//     <o8.23>     PCTIM3: Timer 3 power/clock enable
;//     <o8.22>     PCTIM2: Timer 2 power/clock enable
;//     <o8.21>     PCSSP0: SSP interface 0 power/clock enable
;//     <o8.19>     PCI2C1: I2C interface 1 power/clock enable
;//     <o8.14>     PCAN2: CAN controller 2 power/clock enable
;//     <o8.13>     PCAN1: CAN controller 1 power/clock enable
;//     <o8.12>     PCAD: A/D converter power/clock enable
;//     <o8.11>     PCEMC: External memory controller power/clock enable
;//     <o8.10>     PCSSP1: SSP interface 1 power/clock enable
;//     <o8.9>      PCRTC: RTC power/clock enable
;//     <o8.8>      PCSPI: SPI interface power/clock enable
;//     <o8.7>      PCI2C0: I2C interface 0 power/clock enable
;//     <o8.6>      PCPWM1: PWM 1 power/clock enable
;//     <o8.4>      PCUART1: UART 1 power/clock enable
;//     <o8.3>      PCUART0: UART 0 power/clock enable
;//     <o8.2>      PCTIM1: Timer/Counter 1 power/clock enable
;//     <o8.1>      PCTIM0: Timer/Counter 0 power/clock enable
;//   </h>
;// </e>
CLOCK_SETUP     EQU     1
SCS_Val         EQU     0x00000020
CLKSRCSEL_Val   EQU     0x00000001
PLLCFG_Val      EQU     0x0000000B
CCLKCFG_Val     EQU     0x00000005
USBCLKCFG_Val   EQU     0x00000005
PCLKSEL0_Val    EQU     0x00000000
PCLKSEL1_Val    EQU     0x00000000
PCONP_Val       EQU     0x04280FDE

;----------------------- Memory Accelerator Module (MAM) Definitions -----------

MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
MAMCR_OFS       EQU     0x00            ; MAM Control Offset
MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset

;// <e> MAM Setup
;//   <o1.0..1>   MAM Control
;//               <0=> Disabled
;//               <1=> Partially Enabled
;//               <2=> Fully Enabled
;//               <i> Mode
;//   <o2.0..2>   MAM Timing
;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 3
;//               <4=> 4         <5=> 5   <6=> 6   <7=> 7
;//               <i> Fetch Cycles
;// </e>
MAM_SETUP       EQU     1
MAMCR_Val       EQU     0x00000002
MAMTIM_Val      EQU     0x00000004


;----------------------- Pin Connect Block Definitions -------------------------

PCB_BASE            EQU 0xE002C000      ; PCB Base Address
PINSEL0_OFS         EQU 0x00            ; PINSEL0  Address Offset
PINSEL1_OFS         EQU 0x04            ; PINSEL1  Address Offset
PINSEL2_OFS         EQU 0x08            ; PINSEL2  Address Offset
PINSEL3_OFS         EQU 0x0C            ; PINSEL3  Address Offset
PINSEL4_OFS         EQU 0x10            ; PINSEL4  Address Offset
PINSEL5_OFS         EQU 0x14            ; PINSEL5  Address Offset
PINSEL6_OFS         EQU 0x18            ; PINSEL6  Address Offset
PINSEL7_OFS         EQU 0x1C            ; PINSEL7  Address Offset
PINSEL8_OFS         EQU 0x20            ; PINSEL8  Address Offset
PINSEL9_OFS         EQU 0x24            ; PINSEL9  Address Offset
PINSEL10_OFS        EQU 0x28            ; PINSEL10 Address Offset


;----------------------- External Memory Controller (EMC) Definitons -----------

EMC_BASE            EQU 0xFFE08000      ; EMC Base Address

EMC_CTRL_OFS        EQU 0x000           ; EMCControl
EMC_STAT_OFS        EQU 0x004           ; EMCStatus
EMC_CONFIG_OFS      EQU 0x008           ; EMCConfig
EMC_STA_CFG0_OFS    EQU 0x200           ; EMCStaticConfig0
EMC_STA_WWEN0_OFS   EQU 0x204           ; EMCStaticWaitWen0
EMC_STA_WOEN0_OFS   EQU 0x208           ; EMCStaticWaitOen0
EMC_STA_WRD0_OFS    EQU 0x20C           ; EMCStaticWaitRd0
EMC_STA_WPAGE0_OFS  EQU 0x210           ; EMCStaticWaitPage0
EMC_STA_WWR0_OFS    EQU 0x214           ; EMCStaticWaitWr0
EMC_STA_WTURN0_OFS  EQU 0x218           ; EMCStaticWaitTurn0
EMC_STA_CFG1_OFS    EQU 0x220           ; EMCStaticConfig1
EMC_STA_WWEN1_OFS   EQU 0x224           ; EMCStaticWaitWen1
EMC_STA_WOEN1_OFS   EQU 0x228           ; EMCStaticWaitOen1
EMC_STA_WRD1_OFS    EQU 0x22C           ; EMCStaticWaitRd1
EMC_STA_WPAGE1_OFS  EQU 0x230           ; EMCStaticWaitPage1
EMC_STA_WWR1_OFS    EQU 0x234           ; EMCStaticWaitWr1
EMC_STA_WTURN1_OFS  EQU 0x238           ; EMCStaticWaitTurn1
EMC_STA_EXT_W_OFS   EQU 0x880           ; EMCStaticExtendedWait

BUFEN_Const         EQU (1 << 19)       ; Buffer enable bit
EMC_PCONP_Const     EQU (1 << 11)       ; PCONP val to enable power for EMC

; External Memory Pins definitions
; pin functions for external memory interfacing
EMC_PINSEL6_Val     EQU 0x00005555      ; D0 .. D7
EMC_PINSEL8_Val     EQU 0x55555555      ; A0 .. A15
EMC_PINSEL9_Val     EQU 0x50090000;     ; !OE, !WE (BLS0 because of errata), !CS0, !CS1

;//     External Memory Controller Setup (EMC) ---------------------------------
;// <e> External Memory Controller Setup (EMC)
EMC_SETUP           EQU 1

;//   <h> EMC Control Register (EMCControl)
;//     <i> Controls operation of the memory controller
;//     <o0.2> L: Low-power mode enable
;//     <o0.1> M: Address mirror enable
;//     <o0.0> E: EMC enable
;//   </h>
EMC_CTRL_Val        EQU 0x00000001

;//   <h> EMC Configuration Register (EMCConfig)
;//     <o0.0> Endian mode
;//       <0=> Little-endian
;//       <1=> Big-endian
;//   </h>
EMC_CONFIG_Val      EQU 0x00000000

;//       Configure External Bus Behaviour for Static CS0 Area -----------------
;//   <e> Configure External Bus Behaviour for Static CS0 Area
EMC_STACS0_SETUP    EQU 1

;//     <h> Static Memory Configuration Register (EMCStaticConfig0)
;//       <i> Defines the configuration information for the static memory CS0
;//       <o0.20> WP: Write protect
;//       <o0.19> B: Write buffer enable
;//       <o0.8> EW: Extended wait enable
;//       <o0.6> PC: Chip select polarity
;//         <0=> Active LOW chip select
;//         <1=> Active HIGH chip select
;//       <o0.3> PM: Async page mode enable
;//       <o0.0..1> MW: Memory width
;//         <0=> 8 bit
;//         <1=> 16 bit
;//         <2=> 32 bit
;//     </h>
EMC_STA_CFG0_Val    EQU 0x00000000

;//     <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0)
;//       <i> Selects the delay from CS0 to write enable
;//       <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WWEN0_Val   EQU 0x00000002

;//     <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0)
;//       <i> Selects the delay from CS0 or address change, whichever is later, to output enable
;//       <o.0..3> WAITOEN: Wait output enable <0-15>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WOEN0_Val   EQU 0x00000002
                                      
;//     <h> Static Memory Read Delay Register (EMCStaticWaitRd0)
;//       <i> Selects the delay from CS0 to a read access
;//       <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WRD0_Val    EQU 0x0000001F

;//     <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
;//       <i> Selects the delay for asynchronous page mode sequential accesses for CS0
;//       <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WPAGE0_Val  EQU 0x0000001F

;//     <h> Static Memory Write Delay Register (EMCStaticWaitWr0)
;//       <i> Selects the delay from CS0 to a write access
;//       <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WWR0_Val    EQU 0x0000001F

;//     <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0)
;//       <i> Selects the number of bus turnaround cycles for CS0
;//       <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WTURN0_Val  EQU 0x0000000F

;//   </e> End of Static Setup for Static CS0 Area

;//       Configure External Bus Behaviour for Static CS1 Area -----------------
;//   <e> Configure External Bus Behaviour for Static CS1 Area
EMC_STACS1_SETUP    EQU 0

;//     <h> Static Memory Configuration Register (EMCStaticConfig1)
;//       <i> Defines the configuration information for the static memory CS1
;//       <o0.20> WP: Write protect
;//       <o0.19> B: Write buffer enable
;//       <o0.8> EW: Extended wait enable
;//       <o0.6> PC: Chip select polarity
;//         <0=> Active LOW chip select
;//         <1=> Active HIGH chip select
;//       <o0.3> PM: Async page mode enable
;//       <o0.0..1> MW: Memory width
;//         <0=> 8 bit
;//         <1=> 16 bit
;//         <2=> 32 bit
;//     </h>
EMC_STA_CFG1_Val    EQU 0x00000000

;//     <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1)
;//       <i> Selects the delay from CS1 to write enable
;//       <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WWEN1_Val   EQU 0x00000000

;//     <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1)
;//       <i> Selects the delay from CS1 or address change, whichever is later, to output enable
;//       <o.0..3> WAITOEN: Wait output enable <0-15>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WOEN1_Val   EQU 0x00000000
                                      
;//     <h> Static Memory Read Delay Register (EMCStaticWaitRd1)
;//       <i> Selects the delay from CS1 to a read access
;//       <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WRD1_Val    EQU 0x0000001F

;//     <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
;//       <i> Selects the delay for asynchronous page mode sequential accesses for CS1
;//       <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WPAGE1_Val  EQU 0x0000001F

;//     <h> Static Memory Write Delay Register (EMCStaticWaitWr1)
;//       <i> Selects the delay from CS1 to a write access
;//       <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WWR1_Val    EQU  0x0000001F

;//     <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1)
;//       <i> Selects the number of bus turnaround cycles for CS1
;//       <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;//         <i> The delay is in CCLK cycles
;//     </h>
EMC_STA_WTURN1_Val  EQU 0x0000000F

;//   </e> End of Static Setup for Static CS1 Area

;//   <h> Static Memory Extended Wait Register (EMCStaticExtendedWait)
;//     <i> Time long static memory read and write transfers
;//     <o.0..9> EXTENDEDWAIT: Extended wait time out <1-64><#-1>
;//       <i> The delay is in (16 * CCLK) cycles
;//   </h>
EMC_STA_EXT_W_Val   EQU 0x00000000

;// </e> End of EMC Setup


; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.