/* linux/arch/arm/mach-s3c2410/irq.c * * Copyright (c) 2003,2004 Simtec Electronics *	Ben Dooks <ben@simtec.co.uk> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA * * Changelog: * *   22-Jul-2004  Ben Dooks <ben@simtec.co.uk> *                Fixed compile warnings * *   22-Jul-2004  Roc Wu <cooloney@yahoo.com.cn> *                Fixed s3c_extirq_type * *   21-Jul-2004  Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> *                Addition of ADC/TC demux * *   04-Oct-2004  Klaus Fetscher <k.fetscher@fetron.de> *		  Fix for set_irq_type() on low EINT numbers * *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk> *		  Tidy up KF's patch and sort out new release * *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk> *		  Add support for power management controls * *   04-Nov-2004  Ben Dooks *		  Fix standard IRQ wake for EINT0..4 and RTC*/#include <linux/init.h>#include <linux/module.h>#include <linux/interrupt.h>#include <linux/ioport.h>#include <linux/ptrace.h>#include <linux/sysdev.h>#include <asm/hardware.h>#include <asm/irq.h>#include <asm/io.h>#include <asm/mach/irq.h>#include <asm/arch/regs-irq.h>#include <asm/arch/regs-gpio.h>#include "pm.h"#define irqdbf(x...)#define irqdbf2(x...)#define EXTINT_OFF (IRQ_EINT4 - 4)/* wakeup irq control */#ifdef CONFIG_PM/* state for IRQs over sleep *//* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources * * set bit to 1 in allow bitfield to enable the wakeup settings on it*/unsigned long s3c_irqwake_intallow	= 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;unsigned long s3c_irqwake_intmask	= 0xffffffffL;unsigned long s3c_irqwake_eintallow	= 0x0000fff0L;unsigned long s3c_irqwake_eintmask	= 0xffffffffL;static ints3c_irq_wake(unsigned int irqno, unsigned int state){	unsigned long irqbit = 1 << (irqno - IRQ_EINT0);	if (!(s3c_irqwake_intallow & irqbit))		return -ENOENT;	printk(KERN_INFO "wake %s for irq %d\n",	       state ? "enabled" : "disabled", irqno);	if (!state)		s3c_irqwake_intmask |= irqbit;	else		s3c_irqwake_intmask &= ~irqbit;	return 0;}static ints3c_irqext_wake(unsigned int irqno, unsigned int state){	unsigned long bit = 1L << (irqno - EXTINT_OFF);	if (!(s3c_irqwake_eintallow & bit))		return -ENOENT;	printk(KERN_INFO "wake %s for irq %d\n",	       state ? "enabled" : "disabled", irqno);	if (!state)		s3c_irqwake_eintmask |= bit;	else		s3c_irqwake_eintmask &= ~bit;	return 0;}#else#define s3c_irqext_wake NULL#define s3c_irq_wake NULL#endifstatic voids3c_irq_mask(unsigned int irqno){	unsigned long mask;	irqno -= IRQ_EINT0;	mask = __raw_readl(S3C2410_INTMSK);	mask |= 1UL << irqno;	__raw_writel(mask, S3C2410_INTMSK);}static inline voids3c_irq_ack(unsigned int irqno){	unsigned long bitval = 1UL << (irqno - IRQ_EINT0);	__raw_writel(bitval, S3C2410_SRCPND);	__raw_writel(bitval, S3C2410_INTPND);}static inline voids3c_irq_maskack(unsigned int irqno){	unsigned long bitval = 1UL << (irqno - IRQ_EINT0);	unsigned long mask;	mask = __raw_readl(S3C2410_INTMSK);	__raw_writel(mask|bitval, S3C2410_INTMSK);	__raw_writel(bitval, S3C2410_SRCPND);	__raw_writel(bitval, S3C2410_INTPND);}static voids3c_irq_unmask(unsigned int irqno){	unsigned long mask;	if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)		irqdbf2("s3c_irq_unmask %d\n", irqno);	irqno -= IRQ_EINT0;	mask = __raw_readl(S3C2410_INTMSK);	mask &= ~(1UL << irqno);	__raw_writel(mask, S3C2410_INTMSK);}static struct irqchip s3c_irq_level_chip = {	.ack	   = s3c_irq_maskack,	.mask	   = s3c_irq_mask,	.unmask	   = s3c_irq_unmask,	.wake	   = s3c_irq_wake};static struct irqchip s3c_irq_chip = {	.ack	   = s3c_irq_ack,	.mask	   = s3c_irq_mask,	.unmask	   = s3c_irq_unmask,	.wake	   = s3c_irq_wake};/* S3C2410_EINTMASK * S3C2410_EINTPEND */static voids3c_irqext_mask(unsigned int irqno){	unsigned long mask;	irqno -= EXTINT_OFF;	mask = __raw_readl(S3C2410_EINTMASK);	mask |= ( 1UL << irqno);	__raw_writel(mask, S3C2410_EINTMASK);	if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {		/* check to see if all need masking */		if ((mask & (0xf << 4)) == (0xf << 4)) {			/* all masked, mask the parent */			s3c_irq_mask(IRQ_EINT4t7);		}	} else {		/* todo: the same check as above for the rest of the irq regs...*/	}}static voids3c_irqext_ack(unsigned int irqno){	unsigned long req;	unsigned long bit;	unsigned long mask;	bit = 1UL << (irqno - EXTINT_OFF);	mask = __raw_readl(S3C2410_EINTMASK);	__raw_writel(bit, S3C2410_EINTPEND);	req = __raw_readl(S3C2410_EINTPEND);	req &= ~mask;	/* not sure if we should be acking the parent irq... */	if (irqno <= IRQ_EINT7 ) {		if ((req & 0xf0) == 0)			s3c_irq_ack(IRQ_EINT4t7);	} else {		if ((req >> 8) == 0)			s3c_irq_ack(IRQ_EINT8t23);	}}static voids3c_irqext_unmask(unsigned int irqno){	unsigned long mask;	irqno -= EXTINT_OFF;	mask = __raw_readl(S3C2410_EINTMASK);	mask &= ~( 1UL << irqno);	__raw_writel(mask, S3C2410_EINTMASK);	s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);}static ints3c_irqext_type(unsigned int irq, unsigned int type){	unsigned long extint_reg;	unsigned long gpcon_reg;	unsigned long gpcon_offset, extint_offset;	unsigned long newvalue = 0, value;	if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))	{		gpcon_reg = S3C2410_GPFCON;		extint_reg = S3C2410_EXTINT0;		gpcon_offset = (irq - IRQ_EINT0) * 2;		extint_offset = (irq - IRQ_EINT0) * 4;	}	else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))	{		gpcon_reg = S3C2410_GPFCON;		extint_reg = S3C2410_EXTINT0;		gpcon_offset = (irq - (EXTINT_OFF)) * 2;		extint_offset = (irq - (EXTINT_OFF)) * 4;	}	else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))	{		gpcon_reg = S3C2410_GPGCON;		extint_reg = S3C2410_EXTINT1;		gpcon_offset = (irq - IRQ_EINT8) * 2;		extint_offset = (irq - IRQ_EINT8) * 4;	}	else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))	{		gpcon_reg = S3C2410_GPGCON;		extint_reg = S3C2410_EXTINT2;		gpcon_offset = (irq - IRQ_EINT8) * 2;		extint_offset = (irq - IRQ_EINT16) * 4;	} else		return -1;	/* Set the GPIO to external interrupt mode */	value = __raw_readl(gpcon_reg);	value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);	__raw_writel(value, gpcon_reg);	/* Set the external interrupt to pointed trigger type */	switch (type)	{		case IRQT_NOEDGE:			printk(KERN_WARNING "No edge setting!\n");			break;		case IRQT_RISING:			newvalue = S3C2410_EXTINT_RISEEDGE;			break;		case IRQT_FALLING:			newvalue = S3C2410_EXTINT_FALLEDGE;			break;		case IRQT_BOTHEDGE:			newvalue = S3C2410_EXTINT_BOTHEDGE;			break;		case IRQT_LOW:			newvalue = S3C2410_EXTINT_LOWLEV;			break;		case IRQT_HIGH:			newvalue = S3C2410_EXTINT_HILEV;			break;		default:			printk(KERN_ERR "No such irq type %d", type);			return -1;	}	value = __raw_readl(extint_reg);	value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);	__raw_writel(value, extint_reg);	return 0;}static struct irqchip s3c_irqext_chip = {	.mask	    = s3c_irqext_mask,	.unmask	    = s3c_irqext_unmask,	.ack	    = s3c_irqext_ack,	.type	    = s3c_irqext_type,	.wake	    = s3c_irqext_wake};static struct irqchip s3c_irq_eint0t4 = {	.ack	   = s3c_irq_ack,	.mask	   = s3c_irq_mask,	.unmask	   = s3c_irq_unmask,	.wake	   = s3c_irq_wake,	.type	   = s3c_irqext_type,};/* mask values for the parent registers for each of the interrupt types */#define INTMSK_UART0	 (1UL << (IRQ_UART0 - IRQ_EINT0))#define INTMSK_UART1	 (1UL << (IRQ_UART1 - IRQ_EINT0))#define INTMSK_UART2	 (1UL << (IRQ_UART2 - IRQ_EINT0))#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))#define INTMSK_LCD	 (1UL << (IRQ_LCD - IRQ_EINT0))static inline voids3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,		int subcheck){	unsigned long mask;	unsigned long submask;	submask = __raw_readl(S3C2410_INTSUBMSK);	mask = __raw_readl(S3C2410_INTMSK);	submask |= (1UL << (irqno - IRQ_S3CUART_RX0));	/* check to see if we need to mask the parent IRQ */	if ((submask  & subcheck) == subcheck) {		__raw_writel(mask | parentbit, S3C2410_INTMSK);	}	/* write back masks */	__raw_writel(submask, S3C2410_INTSUBMSK);