/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */INT_MODULE_PARM(if_port, 0);#ifdef PCMCIA_DEBUGINT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);#define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)#else#define DEBUG(n, args...)#endif/* ----------------------------------------------------------------------------Function Prototypes---------------------------------------------------------------------------- */static int nmclan_config(struct pcmcia_device *link);static void nmclan_release(struct pcmcia_device *link);static void nmclan_reset(struct net_device *dev);static int mace_config(struct net_device *dev, struct ifmap *map);static int mace_open(struct net_device *dev);static int mace_close(struct net_device *dev);static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);static void mace_tx_timeout(struct net_device *dev);static irqreturn_t mace_interrupt(int irq, void *dev_id);static struct net_device_stats *mace_get_stats(struct net_device *dev);static int mace_rx(struct net_device *dev, unsigned char RxCnt);static void restore_multicast_list(struct net_device *dev);static void set_multicast_list(struct net_device *dev);static const struct ethtool_ops netdev_ethtool_ops;static void nmclan_detach(struct pcmcia_device *p_dev);/* ----------------------------------------------------------------------------nmclan_attach	Creates an "instance" of the driver, allocating local data	structures for one device.  The device is registered with Card	Services.---------------------------------------------------------------------------- */static int nmclan_probe(struct pcmcia_device *link){    mace_private *lp;    struct net_device *dev;    DEBUG(0, "nmclan_attach()\n");    DEBUG(1, "%s\n", rcsid);    /* Create new ethernet device */    dev = alloc_etherdev(sizeof(mace_private));    if (!dev)	    return -ENOMEM;    lp = netdev_priv(dev);    lp->p_dev = link;    link->priv = dev;        spin_lock_init(&lp->bank_lock);    link->io.NumPorts1 = 32;    link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;    link->io.IOAddrLines = 5;    link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;    link->irq.IRQInfo1 = IRQ_LEVEL_ID;    link->irq.Handler = &mace_interrupt;    link->irq.Instance = dev;    link->conf.Attributes = CONF_ENABLE_IRQ;    link->conf.IntType = INT_MEMORY_AND_IO;    link->conf.ConfigIndex = 1;    link->conf.Present = PRESENT_OPTION;    lp->tx_free_frames=AM2150_MAX_TX_FRAMES;    SET_MODULE_OWNER(dev);    dev->hard_start_xmit = &mace_start_xmit;    dev->set_config = &mace_config;    dev->get_stats = &mace_get_stats;    dev->set_multicast_list = &set_multicast_list;    SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);    dev->open = &mace_open;    dev->stop = &mace_close;#ifdef HAVE_TX_TIMEOUT    dev->tx_timeout = mace_tx_timeout;    dev->watchdog_timeo = TX_TIMEOUT;#endif    return nmclan_config(link);} /* nmclan_attach *//* ----------------------------------------------------------------------------nmclan_detach	This deletes a driver "instance".  The device is de-registered	with Card Services.  If it has been released, all local data	structures are freed.  Otherwise, the structures will be freed	when the device is released.---------------------------------------------------------------------------- */static void nmclan_detach(struct pcmcia_device *link){    struct net_device *dev = link->priv;    DEBUG(0, "nmclan_detach(0x%p)\n", link);    if (link->dev_node)	unregister_netdev(dev);    nmclan_release(link);    free_netdev(dev);} /* nmclan_detach *//* ----------------------------------------------------------------------------mace_read	Reads a MACE register.  This is bank independent; however, the	caller must ensure that this call is not interruptable.  We are	assuming that during normal operation, the MACE is always in	bank 0.---------------------------------------------------------------------------- */static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg){  int data = 0xFF;  unsigned long flags;  switch (reg >> 4) {    case 0: /* register 0-15 */      data = inb(ioaddr + AM2150_MACE_BASE + reg);      break;    case 1: /* register 16-31 */      spin_lock_irqsave(&lp->bank_lock, flags);      MACEBANK(1);      data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));      MACEBANK(0);      spin_unlock_irqrestore(&lp->bank_lock, flags);      break;  }  return (data & 0xFF);} /* mace_read *//* ----------------------------------------------------------------------------mace_write	Writes to a MACE register.  This is bank independent; however,	the caller must ensure that this call is not interruptable.  We	are assuming that during normal operation, the MACE is always in	bank 0.---------------------------------------------------------------------------- */static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data){  unsigned long flags;  switch (reg >> 4) {    case 0: /* register 0-15 */      outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);      break;    case 1: /* register 16-31 */      spin_lock_irqsave(&lp->bank_lock, flags);      MACEBANK(1);      outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));      MACEBANK(0);      spin_unlock_irqrestore(&lp->bank_lock, flags);      break;  }} /* mace_write *//* ----------------------------------------------------------------------------mace_init	Resets the MACE chip.---------------------------------------------------------------------------- */static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr){  int i;  int ct = 0;  /* MACE Software reset */  mace_write(lp, ioaddr, MACE_BIUCC, 1);  while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {    /* Wait for reset bit to be cleared automatically after <= 200ns */;    if(++ct > 500)    {    	printk(KERN_ERR "mace: reset failed, card removed ?\n");    	return -1;    }    udelay(1);  }  mace_write(lp, ioaddr, MACE_BIUCC, 0);  /* The Am2150 requires that the MACE FIFOs operate in burst mode. */  mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);  mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */  mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */  /*   * Bit 2-1 PORTSEL[1-0] Port Select.   * 00 AUI/10Base-2   * 01 10Base-T   * 10 DAI Port (reserved in Am2150)   * 11 GPSI   * For this card, only the first two are valid.   * So, PLSCC should be set to   * 0x00 for 10Base-2   * 0x02 for 10Base-T   * Or just set ASEL in PHYCC below!   */  switch (if_port) {    case 1:      mace_write(lp, ioaddr, MACE_PLSCC, 0x02);      break;    case 2:      mace_write(lp, ioaddr, MACE_PLSCC, 0x00);      break;    default:      mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);      /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,	 and the MACE device will automatically select the operating media	 interface port. */      break;  }  mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);  /* Poll ADDRCHG bit */  ct = 0;  while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)  {  	if(++ ct > 500)  	{  		printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");  		return -1;  	}  }  /* Set PADR register */  for (i = 0; i < ETHER_ADDR_LEN; i++)    mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);  /* MAC Configuration Control Register should be written last */  /* Let set_multicast_list set this. */  /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */  mace_write(lp, ioaddr, MACE_MACCC, 0x00);  return 0;} /* mace_init *//* ----------------------------------------------------------------------------nmclan_config	This routine is scheduled to run after a CARD_INSERTION event	is received, to configure the PCMCIA socket, and to make the	ethernet device available to the system.---------------------------------------------------------------------------- */#define CS_CHECK(fn, ret) \  do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)static int nmclan_config(struct pcmcia_device *link){  struct net_device *dev = link->priv;  mace_private *lp = netdev_priv(dev);  tuple_t tuple;  u_char buf[64];  int i, last_ret, last_fn;  kio_addr_t ioaddr;  DEBUG(0, "nmclan_config(0x%p)\n", link);  CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));  CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));  CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));  dev->irq = link->irq.AssignedIRQ;  dev->base_addr = link->io.BasePort1;  ioaddr = dev->base_addr;  /* Read the ethernet address from the CIS. */  tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;  tuple.TupleData = buf;  tuple.TupleDataMax = 64;  tuple.TupleOffset = 0;  tuple.Attributes = 0;  CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));  CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));  memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);  /* Verify configuration by reading the MACE ID. */  {    char sig[2];    sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);    sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);    if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {      DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",	    sig[0], sig[1]);    } else {      printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"	     " be 0x40 0x?9\n", sig[0], sig[1]);      return -ENODEV;    }  }  if(mace_init(lp, ioaddr, dev->dev_addr) == -1)  	goto failed;  /* The if_port symbol can be set when the module is loaded */  if (if_port <= 2)    dev->if_port = if_port;  else    printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");  link->dev_node = &lp->node;  SET_NETDEV_DEV(dev, &handle_to_dev(link));  i = register_netdev(dev);  if (i != 0) {    printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");    link->dev_node = NULL;    goto failed;  }  strcpy(lp->node.dev_name, dev->name);  printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",	 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);  for (i = 0; i < 6; i++)      printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));  return 0;cs_failed:	cs_error(link, last_fn, last_ret);failed:	nmclan_release(link);	return -ENODEV;} /* nmclan_config *//* ----------------------------------------------------------------------------nmclan_release	After a card is removed, nmclan_release() will unregister the	net device, and release the PCMCIA configuration.  If the device	is still open, this will be postponed until it is closed.---------------------------------------------------------------------------- */static void nmclan_release(struct pcmcia_device *link){	DEBUG(0, "nmclan_release(0x%p)\n", link);	pcmcia_disable_device(link);}static int nmclan_suspend(struct pcmcia_device *link){	struct net_device *dev = link->priv;	if (link->open)		netif_device_detach(dev);	return 0;}static int nmclan_resume(struct pcmcia_device *link){	struct net_device *dev = link->priv;	if (link->open) {		nmclan_reset(dev);		netif_device_attach(dev);	}	return 0;}/* ----------------------------------------------------------------------------nmclan_reset	Reset and restore all of the Xilinx and MACE registers.---------------------------------------------------------------------------- */static void nmclan_reset(struct net_device *dev){  mace_private *lp = netdev_priv(dev);#if RESET_XILINX  struct pcmcia_device *link = &lp->link;  conf_reg_t reg;  u_long OrigCorValue;   /* Save original COR value */  reg.Function = 0;  reg.Action = CS_READ;  reg.Offset = CISREG_COR;  reg.Value = 0;  pcmcia_access_configuration_register(link, &reg);  OrigCorValue = reg.Value;  /* Reset Xilinx */  reg.Action = CS_WRITE;  reg.Offset = CISREG_COR;  DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",	OrigCorValue);  reg.Value = COR_SOFT_RESET;  pcmcia_access_configuration_register(link, &reg);  /* Need to wait for 20 ms for PCMCIA to finish reset. */  /* Restore original COR configuration index */  reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);  pcmcia_access_configuration_register(link, &reg);  /* Xilinx is now completely reset along with the MACE chip. */  lp->tx_free_frames=AM2150_MAX_TX_FRAMES;#endif /* #if RESET_XILINX */  /* Xilinx is now completely reset along with the MACE chip. */  lp->tx_free_frames=AM2150_MAX_TX_FRAMES;