Release 5.2.03i - xst F.31Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s --> Reading design: ONE_PULSE_LCD.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Low Level Synthesis  6) Final Report=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : ONE_PULSE_LCD.prjInput Format                       : VERILOGIgnore Synthesis Constraint File   : NOVerilog Search Path                : Verilog Include Directory          : ---- Target ParametersOutput File Name                   : ONE_PULSE_LCDOutput Format                      : NGCTarget Device                      : xc9500---- Source OptionsTop Module Name                    : ONE_PULSE_LCDAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoMux Extraction                     : YESResource Sharing                   : YESComplex Clock Enable Extraction    : YES---- Target OptionsAdd IO Buffers                     : YESEquivalent register Removal        : YESMACRO Preserve                     : YESXOR Preserve                       : YES---- General OptionsOptimization Criterion             : SpeedOptimization Effort                : 1Keep Hierarchy                     : YESRTL Output                         : YesHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintain---- Other Optionscross_clock_analysis               : NOverilog2001                        : YESwysiwyg                            : NO==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "ONE_PULSE_LCD.prj"Compiling include file "ONE_PULSE_LCD.v"Compiling include file "ONE_PULSE.v"Module <ONE_PULSE> compiledModule <LD_EN_DCNT> compiledModule <P_DLY> compiledModule <DELAY> compiledModule <P_DETECT> compiledModule <DFF_R1> compiledModule <DFF_R> compiledModule <TFF> compiledCompiling include file "BIN_BCD_LCD.v"Module <BIN_BCD_LCD> compiledModule <CNT> compiledModule <LCD> compiledModule <BIN_BCD> compiledModule <ONE_PULSE_LCD> compiledCompiling include file "D:/Xilinx52/verilog/src/iSE/unisim_comp.v"WARNING:HDLCompilers:94 - ONE_PULSE_LCD.v line 21 Connection to input port 2 does not match port sizeNo errors in compilation=========================================================================*                            HDL Analysis                               *=========================================================================Analysis of file <ONE_PULSE_LCD.prj> succeeded.  Analyzing module <DFF_R1>.Module <DFF_R1> is correct for synthesis. Analyzing module <DELAY>.Module <DELAY> is correct for synthesis. Analyzing module <TFF>.Module <TFF> is correct for synthesis. Analyzing module <P_DLY>.Module <P_DLY> is correct for synthesis. Analyzing module <LD_EN_DCNT>.Module <LD_EN_DCNT> is correct for synthesis. Analyzing module <DFF_R>.Module <DFF_R> is correct for synthesis. Analyzing module <P_DETECT>.Module <P_DETECT> is correct for synthesis. Analyzing module <ONE_PULSE>.Module <ONE_PULSE> is correct for synthesis. Analyzing module <CNT>.Module <CNT> is correct for synthesis. Analyzing module <BIN_BCD>.Module <BIN_BCD> is correct for synthesis. Analyzing module <LCD>.WARNING:Xst:905 - BIN_BCD_LCD.v line 68: The signals <NUMW, NUMQ, NUMB, NUMS, NUMG> are missing in the sensitivity list of always block.Module <LCD> is correct for synthesis. Analyzing module <BIN_BCD_LCD>.Module <BIN_BCD_LCD> is correct for synthesis. Analyzing top module <ONE_PULSE_LCD>.Module <ONE_PULSE_LCD> is correct for synthesis.WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <DFF_R1>.    Related source file is ONE_PULSE.v.    Found 1-bit register for signal <Q>.    Summary:	inferred   1 D-type flip-flop(s).Unit <DFF_R1> synthesized.Synthesizing Unit <DELAY>.    Related source file is ONE_PULSE.v.    Found 3-bit up counter for signal <Q>.    Summary:	inferred   1 Counter(s).Unit <DELAY> synthesized.Synthesizing Unit <TFF>.    Related source file is ONE_PULSE.v.    Found 1-bit register for signal <QB>.    Summary:	inferred   1 D-type flip-flop(s).Unit <TFF> synthesized.Synthesizing Unit <P_DLY>.    Related source file is ONE_PULSE.v.Unit <P_DLY> synthesized.Synthesizing Unit <LD_EN_DCNT>.    Related source file is ONE_PULSE.v.    Found 8-bit down counter for signal <Q>.    Summary:	inferred   1 Counter(s).Unit <LD_EN_DCNT> synthesized.Synthesizing Unit <DFF_R>.    Related source file is ONE_PULSE.v.    Found 1-bit register for signal <Q>.    Summary:	inferred   1 D-type flip-flop(s).Unit <DFF_R> synthesized.Synthesizing Unit <P_DETECT>.    Related source file is ONE_PULSE.v.Unit <P_DETECT> synthesized.Synthesizing Unit <ONE_PULSE>.    Related source file is ONE_PULSE.v.Unit <ONE_PULSE> synthesized.Synthesizing Unit <CNT>.    Related source file is BIN_BCD_LCD.v.    Found 16-bit up counter for signal <Q>.    Summary:	inferred   1 Counter(s).Unit <CNT> synthesized.Synthesizing Unit <BIN_BCD>.    Related source file is BIN_BCD_LCD.v.WARNING:Xst:646 - Signal <C> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<19>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<18>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<17>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<16>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<15>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<14>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<13>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<12>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<11>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<10>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<9>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<8>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<7>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<6>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<5>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<4>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<3>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<2>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<1>> is assigned but never used.WARNING:Xst:646 - Signal <TEMP<0>> is assigned but never used.WARNING:Xst:646 - Signal <I> is assigned but never used.    Found 4-bit register for signal <BB>.    Found 4-bit register for signal <BG>.    Found 4-bit register for signal <BQ>.    Found 4-bit register for signal <BS>.    Found 4-bit register for signal <BW>.    Found 4-bit adder for signal <$n0000> created at line 117.    Found 4-bit adder for signal <$n0001> created at line 121.    Found 4-bit adder for signal <$n0002> created at line 125.    Found 4-bit adder for signal <$n0003> created at line 129.    Found 4-bit adder for signal <$n0004> created at line 133.    Found 4-bit adder for signal <$n0024> created at line 117.    Found 4-bit adder for signal <$n0025> created at line 121.    Found 4-bit adder for signal <$n0026> created at line 125.    Found 4-bit adder for signal <$n0027> created at line 129.    Found 4-bit adder for signal <$n0028> created at line 133.    Found 4-bit adder for signal <$n0048> created at line 117.    Found 4-bit adder for signal <$n0049> created at line 121.    Found 4-bit adder for signal <$n0050> created at line 125.    Found 4-bit adder for signal <$n0051> created at line 129.