?? psocconfig.lis
字號:
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ 0F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
0000
00FD DAC_D: equ 0FDh ; DAC Data Register (RW)
0000
00FE CPU_SCR1: equ 0FEh ; CPU Status and Control Register #1 (#)
0080 CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
0010 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
0008 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
0004 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
0001 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
0000
00FF CPU_SCR0: equ 0FFh ; CPU Status and Control Register #2 (#)
0080 CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
0000
0000 ; Port 1
0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
0000
0000 ; Port 2
0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
0000
0000 ; Port 3
000C PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (RW)
000D PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (RW)
000E PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (RW)
000F PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00FN: equ 20h ; Function Register (RW)
0021 DBB00IN: equ 21h ; Input Register (RW)
0022 DBB00OU: equ 22h ; Output Register (RW)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01FN: equ 24h ; Function Register (RW)
0025 DBB01IN: equ 25h ; Input Register (RW)
0026 DBB01OU: equ 26h ; Output Register (RW)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02FN: equ 28h ; Function Register (RW)
0029 DCB02IN: equ 29h ; Input Register (RW)
002A DCB02OU: equ 2Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03FN: equ 2Ch ; Function Register (RW)
002D DCB03IN: equ 2Dh ; Input Register (RW)
002E DCB03OU: equ 2Eh ; Output Register (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0060 CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
000C CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
0003 CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
0000
0061 CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
0018 CLK_CR1_ACLK1: equ 18h ; MASK: Digital PSoC block for analog source
0003 CLK_CR1_ACLK0: equ 03h ; MASK: Digital PSoC block for analog source
0000
0003 CLK_CR1_ACLK2: equ 03h ; Deprecated do not use
0000
0062 ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
0080 ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
0000
0063 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
000F AMD_CR0_AMOD0: equ 0Fh ; MASK: Modulation source for analog column 0
0000
0064 CMP_GO_EN: equ 64h ; Comparator Bus To Global Out Enable (RW)
0080 CMP_GO_EN_GOO5: equ 80h ; MASK: Selected Col 1 signal to GOO5
0040 CMP_GO_EN_GOO1: equ 40h ; MASK: Selected Col 1 signal to GOO1
0030 CMP_GO_EN_SEL1: equ 30h ; MASK: Column 1 Signal Select
0008 CMP_GO_EN_GOO4: equ 08h ; MASK: Selected Col 0 signal to GOO4
0004 CMP_GO_EN_GOO0: equ 04h ; MASK: Selected Col 0 signal to GOO0
0003 CMP_GO_EN_SEL0: equ 03h ; MASK: Column 0 Signal Select
0000
0066 AMD_CR1: equ 66h ; Analog Modulator Control Register 1 (RW)
000F AMD_CR1_AMOD1: equ 0Fh ; MASK: Modulation ctrl for analog column 1
0000
0067 ALT_CR0: equ 67h ; Analog Look Up Table (LUT) Register 0 (RW)
00F0 ALT_CR0_LUT1: equ 0F0h ; MASK: Look up table 1 selection
000F ALT_CR0_LUT0: equ 0Fh ; MASK: Look up table 0 selection
0000
006B CLK_CR3: equ 6Bh ; Analog Clock Source Control Register 3 (RW)
0040 CLK_CR3_SYS1: equ 40h ; MASK: Analog Clock 1 selection
0030 CLK_CR3_DIVCLK1: equ 30h ; MASK: Analog Clock 1 divider
0004 CLK_CR3_SYS0: equ 04h ; MASK: Analog Clock 0 selection
0003 CLK_CR3_DIVCLK0: equ 03h ; MASK: Analog Clock 0 divider
0000
0000 ;------------------------------------------------
0000 ; Global Digital Interconnects
0000 ;------------------------------------------------
0000
00D0 GDI_O_IN: equ 0D0h ; Global Dig Interconnect Odd Inputs Reg (RW)
00D1 GDI_E_IN: equ 0D1h ; Global Dig Interconnect Even Inputs Reg (RW)
00D2 GDI_O_OU: equ 0D2h ; Global Dig Interconnect Odd Outputs Reg (RW)
00D3 GDI_E_OU: equ 0D3h ; Global Dig Interconnect Even Outputs Reg (RW)
0000
0000 ;------------------------------------------------
0000 ; Analog Mux Bus Port Enable Bits
0000 ;------------------------------------------------
00D8 MUX_CR0: equ 0D8h ; Analog Mux Port 0 Bit Enables Register
00D9 MUX_CR1: equ 0D9h ; Analog Mux Port 1 Bit Enables Register
00DA MUX_CR2: equ 0DAh ; Analog Mux Port 2 Bit Enables Register
00DB MUX_CR3: equ 0DBh ; Analog Mux Port 3 Bit Enables Register
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
00DD OSC_GO_EN: equ 0DDh ; Oscillator to Global Outputs Enable Register (RW)
0080 OSC_GO_EN_SLPINT: equ 80h ; Enable Sleep Timer onto GOE[7]
0040 OSC_GO_EN_VC3: equ 40h ; Enable VC3 onto GOE[6]
0020 OSC_GO_EN_VC2: equ 20h ; Enable VC2 onto GOE[5]
0010 OSC_GO_EN_VC1: equ 10h ; Enable VC1 onto GOE[4]
0008 OSC_GO_EN_SYSCLKX2: equ 08h ; Enable 2X SysClk onto GOE[3]
0004 OSC_GO_EN_SYSCLK: equ 04h ; Enable 1X SysClk onto GOE[2]
0002 OSC_GO_EN_CLK24M: equ 02h ; Enable 24 MHz clock onto GOE[1]
0001 OSC_GO_EN_CLK32K: equ 01h ; Enable 32 kHz clock onto GOE[0]
0000
00DE OSC_CR4: equ 0DEh ; Oscillator Control Register 4 (RW)
0003 OSC_CR4_VC3SEL: equ 03h ; MASK: System VC3 Clock source
0000
00DF OSC_CR3: equ 0DFh ; Oscillator Control Register 3 (RW)
0000
00E0 OSC_CR0: equ 0E0h ; System Oscillator Control Register 0 (RW)
0080 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
0040 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ 0E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ 0F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ 0E2h ; Oscillator Control Register 2 (RW)
0080 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ 0E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ 0E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_NOWRITE: equ 08h ; MASK: Vcc below Flash Write level
0004 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
0002 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
0001 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
0000
00E5 ADC0_TR: equ 0E5h ; ADC Column 0 Trim Register
00E6 ADC1_TR: equ 0E6h ; ADC Column 1 Trim Register
0000
00E8 IMO_TR: equ 0E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ 0E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ 0EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ 0EBh ; External Oscillator Trim Register (W)
0000
00FA FLS_PR1: equ 0FAh ; Flash Program Register 1 (RW)
0003 FLS_PR1_BANK: equ 03h ; MASK: Select Active Flash Bank
0000
00FD DAC_CR: equ 0FDh ; Analog Mux DAC Control Register
0008 DAC_CR_IRANGE: equ 08h ; MASK: Sets the DAC Range low or high
0006 DAC_CR_OSCMODE: equ 06h ; MASK: Defines the reset mode for AMux
0001 DAC_CR_ENABLE: equ 01h ; MASK: Enable/Disable DAC function
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
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