?? csdhl.lis
字號:
;;*****************************************************************************
;; FILENAME: CSDHL.asm
;; @Versions@
;; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
;;
;; DESCRIPTION: CSD User Module high level software
;; implementation file for the 21x34 PSoC family of devices.
;;-----------------------------------------------------------------------------
;; Copyright (c) Cypress Semiconductor 2000-2006. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************
00C0 FLAG_PGMODE_MASK: equ 0C0h ; Paging control for > 256 bytes of RAM
0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
00C0 FLAG_PGMODE_3: equ 0C0h ; Direct to CUR_PP page, indexed to STK_PP page
0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
00C0 FLAG_PGMODE_11b: equ 0C0h ; Same as PGMODE_3
0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
0008 FLAG_SUPER: equ 08h ; Supervisor Mode
0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ;-------------------------------------
0000 ; Analog Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0061 AMUXCFG: equ 61h ; Analog MUX Configuration
0030 AMUXCFG_INTCAP: equ 30h ;
000E AMUXCFG_MUXCLK: equ 0Eh ;
0001 AMUXCFG_EN: equ 01h ;
0000
0062 PWM_CR: equ 62h ; Pulse-Width Modulator Control
0038 PWM_CR_HIGH: equ 38h ; MASK: PWM high time
0006 PWM_CR_LOW: equ 06h ; MASK: PWM low time
0001 PWM_CR_EN: equ 01h ; MASK: Enable/Disable PWM function
0000
0064 CMP_CR0: equ 64h ; Analog Comparator Bus Register (#)
0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
0000
0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
0020 CMP_CR1_CLDIS1: equ 20h ; MASK: Column 1 comparator output latch
0010 CMP_CR1_CLDIS0: equ 10h ; MASK: Column 0 comparator output latch
0000
0068 ADC0_CR: equ 68h ; Analog Column 0 Configuration
0080 ADC0_CR_CMPST: equ 80h ;
0040 ADC0_CR_LOREN: equ 40h ;
0020 ADC0_CR_SHEN: equ 20h ;
0008 ADC0_CR_CBSRC: equ 08h ;
0004 ADC0_CR_ADCM: equ 04h ;
0001 ADC0_CR_EN: equ 01h ;
0000
0069 ADC1_CR: equ 69h ; Analog Column 1 Configuration
0080 ADC1_CR_CMPST: equ 80h ;
0040 ADC1_CR_LOREN: equ 40h ;
0020 ADC1_CR_SHEN: equ 20h ;
0008 ADC1_CR_CBSRC: equ 08h ;
0004 ADC1_CR_ADCM: equ 04h ;
0001 ADC1_CR_EN: equ 01h ;
0000
0000 ; Continuous Time PSoC block Type E Row 0 Col 0
0072 ACE00CR1: equ 72h ; Control register 1 (RW)
0073 ACE00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type E Row 0 Col 1
0076 ACE01CR1: equ 76h ; Control register 1 (RW)
0077 ACE01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType E Row 1 Col 0
0080 ASE10CR0: equ 80h ; Control register 0 (RW)
0000
0000 ; Switched Cap PSoC blockType E Row 1 Col 1
0084 ASE11CR0: equ 84h ; Control register 0 (RW)
0000
0000 ;-----------------------------------------------
0000 ; Global General Purpose Data Registers
0000 ;-----------------------------------------------
006C TMP_DR0: equ 6Ch ; Temporary Data Register 0 (RW)
006D TMP_DR1: equ 6Dh ; Temporary Data Register 1 (RW)
006E TMP_DR2: equ 6Eh ; Temporary Data Register 2 (RW)
006F TMP_DR3: equ 6Fh ; Temporary Data Register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; Row Digital Interconnects
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
0000
00B0 RDI0RI: equ 0B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
00B1 RDI0SYN: equ 0B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
00B2 RDI0IS: equ 0B2h ; Row 0 Input Select Register (RW)
00B3 RDI0LT0: equ 0B3h ; Row 0 Look Up Table Register 0 (RW)
00B4 RDI0LT1: equ 0B4h ; Row 0 Look Up Table Register 1 (RW)
00B5 RDI0RO0: equ 0B5h ; Row 0 Output Register 0 (RW)
00B6 RDI0RO1: equ 0B6h ; Row 0 Output Register 1 (RW)
0000
0000 ;-----------------------------------------------
0000 ; Ram Page Pointers
0000 ;-----------------------------------------------
00D0 CUR_PP: equ 0D0h ; Current Page Pointer
00D1 STK_PP: equ 0D1h ; Stack Page Pointer
00D3 IDX_PP: equ 0D3h ; Index Page Pointer
00D4 MVR_PP: equ 0D4h ; MVI Read Page Pointer
00D5 MVW_PP: equ 0D5h ; MVI Write Page Pointer
0000
0000 ;------------------------------------------------
0000 ; I2C Configuration Registers
0000 ;------------------------------------------------
00D6 I2C_CFG: equ 0D6h ; I2C Configuration Register (RW)
0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
0000
00D7 I2C_SCR: equ 0D7h ; I2C Status and Control Register (#)
0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
0000
00D8 I2C_DR: equ 0D8h ; I2C Data Register (RW)
0000
00D9 I2C_MSCR: equ 0D9h ; I2C Master Status and Control Register (#)
0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ 0DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ 0DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DD INT_CLR3: equ 0DDh ; Interrupt Clear Register 3 (RW)
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