?? lcd.lis
字號(hào):
0000 ;------------------------------------------------
0000 ; I2C Configuration Registers
0000 ;------------------------------------------------
00D6 I2C_CFG: equ 0D6h ; I2C Configuration Register (RW)
0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
0000
00D7 I2C_SCR: equ 0D7h ; I2C Status and Control Register (#)
0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
0000
00D8 I2C_DR: equ 0D8h ; I2C Data Register (RW)
0000
00D9 I2C_MSCR: equ 0D9h ; I2C Master Status and Control Register (#)
0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ 0DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ 0DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DD INT_CLR3: equ 0DDh ; Interrupt Clear Register 3 (RW)
0000 ; Use INT_MSK3 bit field masks
0000
00DE INT_MSK3: equ 0DEh ; I2C and Software Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0001 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
0000
00E0 INT_MSK0: equ 0E0h ; General Interrupt Mask Register (RW)
0080 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0004 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ 0E1h ; Digital PSoC block Mask Register (RW)
0008 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
0004 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
0002 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
0001 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
0000
00E2 INT_VC: equ 0E2h ; Interrupt vector register (RC)
00E3 RES_WDT: equ 0E3h ; Watch Dog Timer Register (W)
0000
0000 ; DECIMATOR Control Registers
00E6 DEC_CR0: equ 0E6h ; Data Control Register 0 (RW)
00E7 DEC_CR1: equ 0E7h ; Data Control Register 1 (RW)
0000
0000 ;------------------------------------------------------
0000 ; System Status and Control Registers
0000 ;
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ 0F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
0000
00FD DAC_D: equ 0FDh ; DAC Data Register (RW)
0000
00FE CPU_SCR1: equ 0FEh ; CPU Status and Control Register #1 (#)
0080 CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
0010 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
0008 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
0004 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
0001 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
0000
00FF CPU_SCR0: equ 0FFh ; CPU Status and Control Register #2 (#)
0080 CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
0000
0000 ; Port 1
0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
0000
0000 ; Port 2
0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
0000
0000 ; Port 3
000C PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (RW)
000D PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (RW)
000E PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (RW)
000F PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00FN: equ 20h ; Function Register (RW)
0021 DBB00IN: equ 21h ; Input Register (RW)
0022 DBB00OU: equ 22h ; Output Register (RW)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01FN: equ 24h ; Function Register (RW)
0025 DBB01IN: equ 25h ; Input Register (RW)
0026 DBB01OU: equ 26h ; Output Register (RW)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02FN: equ 28h ; Function Register (RW)
0029 DCB02IN: equ 29h ; Input Register (RW)
002A DCB02OU: equ 2Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03FN: equ 2Ch ; Function Register (RW)
002D DCB03IN: equ 2Dh ; Input Register (RW)
002E DCB03OU: equ 2Eh ; Output Register (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0060 CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
000C CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
0003 CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
0000
0061 CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
0018 CLK_CR1_ACLK1: equ 18h ; MASK: Digital PSoC block for analog source
0003 CLK_CR1_ACLK0: equ 03h ; MASK: Digital PSoC block for analog source
0000
0003 CLK_CR1_ACLK2: equ 03h ; Deprecated do not use
0000
0062 ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
0080 ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
0000
0063 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
000F AMD_CR0_AMOD0: equ 0Fh ; MASK: Modulation source for analog column 0
0000
0064 CMP_GO_EN: equ 64h ; Comparator Bus To Global Out Enable (RW)
0080 CMP_GO_EN_GOO5: equ 80h ; MASK: Selected Col 1 signal to GOO5
0040 CMP_GO_EN_GOO1: equ 40h ; MASK: Selected Col 1 signal to GOO1
0030 CMP_GO_EN_SEL1: equ 30h ; MASK: Column 1 Signal Select
0008 CMP_GO_EN_GOO4: equ 08h ; MASK: Selected Col 0 signal to GOO4
0004 CMP_GO_EN_GOO0: equ 04h ; MASK: Selected Col 0 signal to GOO0
0003 CMP_GO_EN_SEL0: equ 03h ; MASK: Column 0 Signal Select
0000
0066 AMD_CR1: equ 66h ; Analog Modulator Control Register 1 (RW)
000F AMD_CR1_AMOD1: equ 0Fh ; MASK: Modulation ctrl for analog column 1
0000
0067 ALT_CR0: equ 67h ; Analog Look Up Table (LUT) Register 0 (RW)
00F0 ALT_CR0_LUT1: equ 0F0h ; MASK: Look up table 1 selection
000F ALT_CR0_LUT0: equ 0Fh ; MASK: Look up table 0 selection
0000
006B CLK_CR3: equ 6Bh ; Analog Clock Source Control Register 3 (RW)
0040 CLK_CR3_SYS1: equ 40h ; MASK: Analog Clock 1 selection
0030 CLK_CR3_DIVCLK1: equ 30h ; MASK: Analog Clock 1 divider
0004 CLK_CR3_SYS0: equ 04h ; MASK: Analog Clock 0 selection
0003 CLK_CR3_DIVCLK0: equ 03h ; MASK: Analog Clock 0 divider
0000
0000 ;------------------------------------------------
0000 ; Global Digital Interconnects
0000 ;------------------------------------------------
0000
00D0 GDI_O_IN: equ 0D0h ; Global Dig Interconnect Odd Inputs Reg (RW)
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