#define CAN_TST_SILENT          0x00000008  // Silent mode
#define CAN_TST_BASIC           0x00000004  // Basic mode

//*****************************************************************************
//
// The following define the bit fields in the CAN_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE           0x0000000F  // Baud rate prescaler extension

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCRQ_BUSY          0x00008000  // Busy flag status
#define CAN_IFCRQ_MNUM_MSK      0x0000003F  // Message Number

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFCMSK_WRNRD        0x00000080  // Write, not Read
#define CAN_IFCMSK_MASK         0x00000040  // Access Mask Bits
#define CAN_IFCMSK_ARB          0x00000020  // Access Arbitration Bits
#define CAN_IFCMSK_CONTROL      0x00000010  // Access Control Bits
#define CAN_IFCMSK_CLRINTPND    0x00000008  // Clear interrupt pending Bit
#define CAN_IFCMSK_TXRQST       0x00000004  // Access Tx request bit (WRNRD=1)
#define CAN_IFCMSK_NEWDAT       0x00000004  // Access New Data bit (WRNRD=0)
#define CAN_IFCMSK_DATAA        0x00000002  // DataA access - bytes 0 to 3
#define CAN_IFCMSK_DATAB        0x00000001  // DataB access - bytes 4 to 7

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK1_MSK          0x0000FFFF  // Identifier Mask

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMSK2_MXTD         0x00008000  // Mask extended identifier
#define CAN_IFMSK2_MDIR         0x00004000  // Mask message direction
#define CAN_IFMSK2_MSK          0x00001FFF  // Mask identifier

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB1_ID           0x0000FFFF  // Identifier

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFARB2_MSGVAL       0x00008000  // Message valid
#define CAN_IFARB2_XTD          0x00004000  // Extended identifier
#define CAN_IFARB2_DIR          0x00002000  // Message direction
#define CAN_IFARB2_ID           0x00001FFF  // Message identifier

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFMCTL_NEWDAT       0x00008000  // New Data
#define CAN_IFMCTL_MSGLST       0x00004000  // Message lost
#define CAN_IFMCTL_INTPND       0x00002000  // Interrupt pending
#define CAN_IFMCTL_UMASK        0x00001000  // Use acceptance mask
#define CAN_IFMCTL_TXIE         0x00000800  // Transmit interrupt enable
#define CAN_IFMCTL_RXIE         0x00000400  // Receive interrupt enable
#define CAN_IFMCTL_RMTEN        0x00000200  // Remote enable
#define CAN_IFMCTL_TXRQST       0x00000100  // Transmit request
#define CAN_IFMCTL_EOB          0x00000080  // End of buffer
#define CAN_IFMCTL_DLC          0x0000000F  // Data length code

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA1_DATA          0x0000FFFF  // Data - bytes 1 and 0

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDA2_DATA          0x0000FFFF  // Data - bytes 3 and 2

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB1_DATA          0x0000FFFF  // Data - bytes 5 and 4

//*****************************************************************************
//
// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2
// registers.
// Note:  All bits may not be available in all registers
//
//*****************************************************************************
#define CAN_IFDB2_DATA          0x0000FFFF  // Data - bytes 7 and 6

//*****************************************************************************
//
// The following define the bit fields in the CAN_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST        0x0000FFFF  // Transmission Request Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST        0x0000FFFF  // Transmission Request Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDATA       0x0000FFFF  // New Data Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDATA       0x0000FFFF  // New Data Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGINT1 register.
//
//*****************************************************************************
#define CAN_MSGINT1_INTPND      0x0000FFFF  // Interrupt Pending Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGINT2 register.
//
//*****************************************************************************
#define CAN_MSGINT2_INTPND      0x0000FFFF  // Interrupt Pending Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGVAL1 register.
//
//*****************************************************************************
#define CAN_MSGVAL1_MSGVAL      0x0000FFFF  // Message Valid Bits

//*****************************************************************************
//
// The following define the bit fields in the CAN_MSGVAL2 register.
//
//*****************************************************************************
#define CAN_MSGVAL2_MSGVAL      0x0000FFFF  // Message Valid Bits

#endif // __HW_CAN_H__