ResetHalt
Delay 200
Stop

; Set VBR to the beginning of what will be SDRAM
; VBR is an absolute CPU register
; SDRAM is at 0x00000000+0x0400000
writecontrolreg 0x0801 0x00000000


; Set RAMBAR = 0x20000001
; RAMBAR is an absolute CPU register
; This is the location of the internal 64k of SRAM on the chip
writecontrolreg 0x0C05 0x20000001

; Set FLASHBAR = 0xF0000001
; FLASHBAR is an absolute CPU register
; This is the location of the internal 64k of SRAM on the chip
writecontrolreg 0x0C04 0xF0000021

; Set PBCDPAR to allow 32-bit SDRAM if the exteranl boot device is 16-bits
writemem.b 0x40100050 0xC0

; Turn off WCR
writemem.b 0x40140000  0x0000

; 2MB FLASH on CS0 at 0xFFE00000

writemem.w 0x40000080   0xFFE0		; CSAR0
writemem.l 0x40000084   0x001F0001	; CSMR0
writemem.w 0x4000008A   0x1980		; CSCR0


delay 1000

; SDRAM
; Like the 5307 and 5407 Cadre 3 boards, this board uses DCR,DACR, DMR to access SDRAM

writemem.w 0x40000040   0x023C     ; 
writemem.l 0x40000048   0x00001300 ;
writemem.l 0x4000004C   0x00FC0001 ;
writemem.l 0x40000048   0x00001308 ;
writemem.l 0x00000000   0x00000000 ;


; Wait a bit
delay 1000;

; Initialize SDRAM with a write 

writemem.l 0x40000048 0x00009300 ;
writemem.l 0x40000048 0x00009340 ;
writemem.l 0x00000400 0x00000000 ;

; Wait a bit more
delay 1000