/************* Revision Controle System Header *************
 *                  GSM Layer 1 software
 * DYNAMIC_CLOCK_7_8_H
 *
 *        Filename dynamic_clock_7_8.h
 *  Copyright 2003 (C) Texas Instruments  
 *
 ************* Revision Controle System Header *************/



/***********************************************************************************************
 *          Only SAMSON/CALYPSO families are considered for dynamic clock configuration.
 ***********************************************************************************************
 *
 *                         CHIPSET = 7 (CALYPSO C05 Rev A)
 *                         CHIPSET = 8 (CALYPSO C05 Rev B)
 *
 ***********************************************************************************************
 *                         Supported clock configuration
 *
 *
 *       CHIPSET                78/78/13    78/78/39   104/104/52    156/78/52   130/130/65
 *                                 (0)         (1)          (2)         (3)         (4)
 *
 *  CALYPSO C05 Rev A     (7)      X            X           NA          NA          NA
 *  CALYPSO C05 Rev B     (8)      X            X           NA          NA          NA
 *        
 *                                (0)--> Not applicable due to API 16-bits read problem
 *
 *           BOARD                CHIPSET                         Access Time (ns)
 *                                                     CS0    CS1    CS2    CS3    CS4    CS5
 *  
 *    EVA4 (RAM)        (6)     CALYPSO C05            100    NA     NA     NA     100    NA
 *    C-Sample (RAM)    (8)     CALYPSO C05            100    100    NA                   NA    (RD108, RD308) FLASH : AM29DL322T-70 (AMD) - SRAM : IC806 ????
 *    C-Sample (FLASH)  (9)     CALYPSO C05            100    100    NA                   NA    (RD108, RD308) FLASH : AM29DL322T-70 (AMD) - SRAM : IC806 ????
 *    D-Sample (RAM)    (40)    CALYPSO C05            85     70     70                   NA    (RD316, RD112) FLASH/SRAM : 28F640W30B70 (Intel) - SRAM : K1S321615M-EE10 (Samsung)
 *    D-Sample (FLASH)  (41)    CALYPSO C05            70     70     85                   NA    (RD316, RD112) FLASH/SRAM : 28F640W30B70 (Intel) - SRAM : K1S321615M-EE10 (Samsung)
 *
 ***********************************************************************************************/

#include "chipset.cfg"
#include "board.cfg"

#if (CHIPSET == 7) || (CHIPSET == 8)
  
  #ifndef _DYNAMIC_CLOCK_7_8_H_
    #define _DYNAMIC_CLOCK_7_8_H_
    
    #ifdef _DYNAMIC_CLOCK_C_

    /***************************************************************************
     *                      C_CLOCK_CFG_78_78_13 configuration
     **************************************************************************/
    /* Not applicable due to API 16-bits read problem */


   /***************************************************************************
    *                       C_CLOCK_CFG_78_78_39 configuration
    **************************************************************************/
    const T_DYNAMIC_CLOCK_CFG d_7_8_78_78_39_clock = 
        {
          /* Index of the present clock configuration */
          C_CLOCK_CFG_78_78_39,

          /* DSP clock in kHz */
          78000,
          
          /* DPLL configuration */
          DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 6,

          /* ARM clock configuration */
          CLKM_SEL_DPLL, 2, CLKM_DISABLE_XP5,

          /* DSP latencies configuration */
          D_LAT_MCU_HOM2SAM,
          D_LAT_MCU_BRIDGE,
          D_LAT_MCU_BEF_FAST_ACCESS,
          D_LAT_DSP_AFTER_SAM,
          D_TRANSFER_RATE,

          /* API-RHEA configuration */
          /* API_WS */
          0, 1,
          /* RHEA Access Factor */
          #if (CHIPSET == 7)
          //  should be 0xFE01 due to DMA limitation at 34MHz
          // Must be updated according to ARM clock configuration
          1, 0,
        #endif
  
        #if (CHIPSET == 8)
              // should be 0xFE00 due to no DMA limitation at 34MHz
              // Must be updated according to ARM clock configuration
          0, 0,
        #endif
  
        /* RHEA Timeout */
          0x7F,
     
          /* EMIF configuration */
          #if (BOARD == 6)
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
            { 2, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS1
            { 4, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 8) // C-Sample RAM
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - External SRAM
            { 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - FLASH
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - Nothing
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 9) // C-Sample FLASH
            { 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - FLASH
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - Nothing
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3 - Parallel IO
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4 - Debug latch
          #elif (BOARD == 40) // D-Sample RAM
            { 4, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - External SRAM
            { 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM 8Mbits
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - FLASH
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #elif (BOARD == 41) // D-Sample FLASH
            { 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - FLASH
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM 8Mbits
            { 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - External SRAM
            { 5, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS3
            { 0, MEM_DVS_8,  MEM_WRITE_EN, 0 }, // CS4
          #else
            #error "This BOARD configuration is not supported"
          #endif
          { 0, MEM_DVS_32,  MEM_WRITE_EN, 0 }, // CS6
          { 0, MEM_DVS_32,  MEM_WRITE_DIS, 0 }, // CS7

        };


    const T_DYNAMIC_CLOCK_CFG * a_dynamic_clock_cfg[C_NB_MAX_CLOCK_CONFIG] = {
                        &d_7_8_78_78_39_clock,          /* 78/78/39 MHz */
                        (T_DYNAMIC_CLOCK_CFG *) NULL,
          };

    #else
      extern const T_DYNAMIC_CLOCK_CFG * a_dynamic_clock_cfg[C_NB_MAX_CLOCK_CONFIG];
    #endif  /* _DYNAMIC_CLOCK_C_ */

  #endif  /* _DYNAMIC_CLOCK_7_8_H_ */

#endif /* CHIPSET == 7 or 8 */