/************* Revision Controle System Header *************
 *                  GSM Layer 1 software
 * DYNAMIC_CLOCK_H
 *
 *        Filename %M%
 *  Copyright 2003 (C) Texas Instruments  
 *
 ************* Revision Controle System Header *************/

#ifndef _DYNAMIC_CLOCK_H_
  #define _DYNAMIC_CLOCK_H_

  #include "chipset.cfg"
  #include "board.cfg"

  /*
   * Only SAMSON/CALYPSO families are considered for dynamic clock configuration.
   */

  #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \
      (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)


    #include "sys_types.h"
    #include "mem.h"
    #if (CHIPSET == 12) || (CHIPSET == 15)
      #include "sys_memif.h"
    #endif

    /* Maximal number of clock configurations */
    #define C_NB_MAX_CLOCK_CONFIG         10

    /* Value of index if no dynamic clock configuration selected */
    #define C_CLOCK_NO_CFG            0xFF
 
    /* Define the indexes of the available clock configurations */
    /* Indexes are defined as : C_CLOCK_CFG_DPLL_DSP_ARM */
    #if (CHIPSET == 15)
    //For Locosto: DSP is 104 MHz and ARM could be 104/52 MHz
    #define C_CLOCK_CFG_104_104_104   0
    #define C_CLOCK_CFG_104_104_52      1
    #else	
    #define C_CLOCK_CFG_78_78_13      0
    #define C_CLOCK_CFG_78_78_39      1
    #define C_CLOCK_CFG_104_104_52    2
    #define C_CLOCK_CFG_156_78_52     3
    #define C_CLOCK_CFG_130_130_65    4
    #endif

    /* Default clock configuration used at initialization */
    #if (CHIPSET == 4)
      /* Samson C07 family */
      #define C_CLOCK_CFG_DEFAULT       C_CLOCK_CFG_78_78_13
      
    #elif (CHIPSET == 7) || (CHIPSET == 8)
      /* Calypso C05 family */
      #define C_CLOCK_CFG_DEFAULT       C_CLOCK_CFG_78_78_39
      
    #elif (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
      /* Calypso C035 family */
      #define C_CLOCK_CFG_DEFAULT       C_CLOCK_CFG_104_104_52
      
    #elif (CHIPSET == 15)
      /* Locosto default configuration is DPLL =104 MHz ARM=104MHz DSP = 104MHz*/
      #define C_CLOCK_CFG_DEFAULT	C_CLOCK_CFG_104_104_104
    #endif

    /* Structure used to define clock configurations               */
    /* Due to chipset and board dependencies, clock configurations */ 
    /* are pre-defined in a table of structures                    */
    typedef struct {
      /* Index of the present clock configuration */
      SYS_UWORD8 d_clock_cfg_index;
      
      /* DSP clock in kHz used in conjunction of d_dsp_cur_clk */
      SYS_UWORD32 d_dsp_clk;
      
      /* DPLL configuration */
      SYS_UWORD16 d_bypass_div;
      SYS_UWORD16 d_dpll_div;
      SYS_UWORD16 d_dpll_mult;

      /* ARM clock configuration */
      SYS_UWORD16 d_arm_clk_source;
     #if (CHIPSET == 15)
        SYS_UWORD16 d_arm_clk_mode;
     #else
       SYS_UWORD16 d_arm_clk_div;
       SYS_UWORD16 d_arm_clk_div_sel;
      #endif
     

      #if CHIPSET == 12
        /* DSP configuration */
        SYS_UWORD16 d_dsp_div_clk;
      #endif

      /* DSP latencies configuration */
      API_SIGNED d_lat_mcu_hom2sam;
      API_SIGNED d_lat_mcu_bridge;
      API_SIGNED d_lat_mcu_bef_fast_access;
      API_SIGNED d_lat_dsp_after_sam;
      API_SIGNED d_transfer_rate;

      /* API-RHEA configuration */
      SYS_UWORD16 d_api_ws_hom;
      SYS_UWORD16 d_api_ws_sam;
      SYS_UWORD16 d_rhea_af_strobe0;
      SYS_UWORD16 d_rhea_af_strobe1;
      SYS_UWORD16 d_rhea_timeout;

      /* EMIF configuration */
      #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
        T_MEMIF_CS_CONFIG d_cs0;
        T_MEMIF_CS_CONFIG d_cs1;
        T_MEMIF_CS_CONFIG d_cs2;
        T_MEMIF_CS_CONFIG d_cs3;
      #elif (CHIPSET == 12)
        T_MEMIF_CS_CONFIG d_cs0;
      #endif
      
      #if ( CHIPSET != 15 )
        T_MEMIF_CS_CONFIG d_cs4;
      #else
	/* Different configuration structure for Locosto */
	T_EMIF_CS_CONFIG d_cs0;
	T_EMIF_CS_CONFIG d_cs3;
      #endif

      #if (CHIPSET == 12)
        T_MEMIF_CS_CONFIG d_cs5;
      #endif

      #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
        T_MEMIF_CS_CONFIG d_cs6;
        T_MEMIF_CS_CONFIG d_cs7;
      #endif


    } T_DYNAMIC_CLOCK_CFG;

    extern T_DYNAMIC_CLOCK_CFG *p_dynamic_clock_cfg;
    extern SYS_UWORD32  d_dsp_cur_clk;   // To store current DSP clock due to DSP latency management

    extern f_dynamic_clock_cfg(SYS_UWORD8 d_clock_cfg);

#define FLASH_OFFSET_ADR 0x06000000
#define SHADOW_OFFSET 0x06000000
#define PSRAM_OFFSET 0x00400000
#define INTRAM_OFFSET 0x08000000

#define MEM8(a) *(volatile unsigned char*) (a)
#define MEM16(a) *(volatile unsigned short*) (a)
#define MEM32(a) *(volatile unsigned long int*) (a)


#define PSRAM_OPERATING_MODE 0	// 0 = burst 1 = async
#define PSRAM_LATENCY_COUNTER 3	// latency code 3 = 4 clocks
#define PSRAM_WAIT_POLARITY 0		// 0 = active low, 1 = active high
#define PSRAM_WAIT_CONFIGURATION 1	// 0 = asserted during delay, 1 = asserted before delay
#define PSRAM_CLOCK_CONFIGURATION 1	// 1 = rising edge
#define PSRAM_OUTPUT_IMPEDANCE 0	// 0 = full drive, 1 = low drive
#define PSRAM_BURST_WRAP 0			// 0 = wrap enable, 1 = wrap disabled
#define PSRAM_BURST_LENGTH 2		// 1 = 4 words, 2 = 8 words, 3 = 16 words, 7 = continous

// For mirror-bit flash:
#define FLASH_WAIT_STATE 3	// code 3 = 5 clocks
#define FLASH_RDY_POLARITY 1		// 0 = active low, 1 = active high
#define FLASH_RDY 1	// 0 = asserted before delay, 1 = asserted during delay
#define FLASH_BURST_WRAP 1			// 1 = wrap enable, 0 = wrap disabled
#define FLASH_BURST_LENGTH 2		// 2 = 8 words, 3 = 16 words, 0 = continous


				 
#define EMIF_BASE 0xfffffb00
#define EMIF_CONF_REG 0x0002
#define EMIF_CFG_CS0 0x0004
#define EMIF_CFG_CS3 0x0010
#define EMIF_DYN_WAIT_REG 0x001c
#define EMIF_ADVANCED_CFG_CS0 0x0014
#define EMIF_ADVANCED_CFG_CS3 0x001a

// SET_EMIF_CONF_REG (WP, FLUSH_PREFETCH, PREFETCH_MODE, PDE, PWD_EN)
// Writes the EMIF configuration register:
//  WP : General write-protect of external memory
//  FLUSH_PREFETCH : Flush the prefetch buffer
//  PREFETCH_MODE : 0 Prefetch off, 1 Instruction and data, 2 instruction only, 3 reserved
//  PDE : Global power down enable signal
//  PWD_EN : EMIF power down enable
#define SET_EMIF_CONF_REG(WP, FLUSH_PREFETCH, PREFETCH_MODE, PDE, PWD_EN) {\
	MEM16 (EMIF_BASE + EMIF_CONF_REG) = \
		((WP)<<6)|\
		((FLUSH_PREFETCH)<<5)|\
		((PREFETCH_MODE)<<3)|\
		((PDE)<<1)|\
		(PWD_EN);}

// SET_EMIF_CFG(CS, BTWST, MEMMODE, WELEN, WRWST, RDWST, RT, FCLKDIV)
// Writes the EMIF chip-select registers:
//  CS : Chip-select to configure
//  BTWST : Number of wait-states from read-to-write
//  MEMMODE : 0 async, 1 burst read, 2 burst read/write
//  WELEN : Length of WE pulse
//  WRWST : Write wait states
//  RDWST : Read wait states
//  RT : re-timing
//  FCLKDIV : 0..3 = divide by 1, 2, 4, 6
#define SET_EMIF_CFG(CS, BTWST, MEMMODE, WELEN, WRWST, RDWST, RT, FCLKDIV) {\
	MEM16 (EMIF_BASE + EMIF_CFG_CS0 + 2 + CS*4) =\
		((BTWST) << 6) |\
		(MEMMODE);\
	MEM16 (EMIF_BASE + EMIF_CFG_CS0 + CS*4) =\
		((WELEN) << 12) |\
		((WRWST) << 8) | \
		((RDWST) << 4) | \
		((RT) << 2) |\
		(FCLKDIV);\
			}
			

// SET_EMIF_ADVANCED_CFG(CS, RC, CLKMSK, BTMODE, ADVHOLD, OEHOLD, OESETUP)
// Writes the advanced chip-select register
//  CS : Chip-select to configure
//  RC : 0 Expect ready one clock before data valid, 1 expect ready in same cycle as data
//  CLKMSK : 0 Clock is sent during writes in synchroneous mode, 1 clock is disabled during writes
//  BTMODE : Mode selection for BTWST
//  ADVHOLD : Hold cycle for address valid
//  OEHOLD : Cycles from OE high to CS high
//  OESETUP : Cycles from CS low to OE low
#define SET_EMIF_ADVANCED_CFG(CS, RC, CLKMSK, BTMODE, ADVHOLD, OEHOLD, OESETUP) {\
	MEM16(EMIF_BASE + EMIF_ADVANCED_CFG_CS0 + CS*2) =\
		((RC)<<11)|\
		((CLKMSK)<<10)|\
		((BTMODE)<<9)|\
		((ADVHOLD)<<8)|\
		((OEHOLD)<<4)|\
		(OESETUP);}

// SET_EMIF_NO_DYN_WAIT(CS, DISABLE) 
// Modifies the dynamic wait state register
//  CS : Chip-select to configure
//  DISABLE : 0 dynamic wait enabled, 1 dynamic wait disabled
#define SET_EMIF_NO_DYN_WAIT(CS, DISABLE) 	MEM16 (EMIF_BASE + EMIF_DYN_WAIT_REG) = (MEM16 (EMIF_BASE + EMIF_DYN_WAIT_REG) & ~(1<<CS)) | (DISABLE<<CS);
  #endif /* SAMSON/CALYPSO families */

#endif /* _DYNAMIC_CLOCK_H_ */