?? int.s
字號(hào):
;
;extern VOID *TCD_System_Stack;
;
.ref _TCD_System_Stack
.ref _TCT_System_Limit
;
;
;/* Define the global data structures that need to be initialized by this
; routine. These structures are used to define the system timer management
; HISR. */
;
;extern VOID *TMD_HISR_Stack_Ptr;
;extern UNSIGNED TMD_HISR_Stack_Size;
;extern INT TMD_HISR_Priority;
;
.ref _TMD_HISR_Stack_Ptr
.ref _TMD_HISR_Stack_Size
.ref _TMD_HISR_Priority
;
;
;/* Define extern function references. */
;
;VOID INC_Initialize(VOID *first_available_memory);
;VOID TCT_Interrupt_Context_Save(VOID);
;VOID TCT_Interrupt_Context_Restore(VOID);
;VOID TCC_Dispatch_LISR(INT vector_number);
;VOID TMT_Timer_Interrupt(void);
;
.ref _INC_Initialize
.ref _TCT_Interrupt_Context_Save
.ref _TCT_Interrupt_Context_Restore
.ref _TCC_Dispatch_LISR
.ref _TMT_Timer_Interrupt
.if CHIPSET == 12 | CHIPSET == 15 ;change for Locosto
;/* Application f_inth_irq_handler, f_inth_fiq_handler */
.ref _f_inth_irq_handler
.ref _f_inth_fiq_handler
.else
;/* Application ISR */
.ref _IQ_IRQ_isr
.ref _IQ_FIQ_isr
.endif
;
; /* Reference pointers defined by the linker */
;
.ref .bss
.ref end
.if OP_L1_STANDALONE = 0
;
;/* Define indirect branching labels for the vector table */
;
.def INT_Undef_Inst
INT_Undef_Inst
B arm_undefined ; Undefined
;
.def INT_Swi
INT_Swi
B arm_swi ; Software Generated
;
.def INT_Abort_Prefetch
INT_Abort_Prefetch
B arm_abort_prefetch ; Abort Prefetch
;
.def INT_Abort_Data
INT_Abort_Data
B arm_abort_data ; Abort Data
;
.def INT_Reserved
INT_Reserved
B arm_reserved ; Reserved
;
.def Vect_IRQ
Vect_IRQ
.if TI_NUC_MONITOR = 1
.if CHIPSET = 12 | CHIPSET = 15
B Vect_IRQ
.else
B _INT_IRQ
.endif
.else
B INT_IRQ
.endif
;
.def Vect_FIQ
Vect_FIQ
.if TI_PROFILER = 1
.if CHIPSET = 12 | CHIPSET = 15
B Vect_FIQ
.else
B _INT_FIQ
.endif
.else
B INT_FIQ
.endif
;
.if PSP_STANDALONE =1
.def INT_Small_Sleep
INT_Small_Sleep
.ref TCT_Schedule_Loop
B TCT_Schedule_Loop
.endif
.endif ; OP_L1_STANDALONE = 0
;
;/*************************************************************************/
;/* */
;/* FUNCTION */
;/* */
;/* INT_Initialize */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function sets up the global system stack variable and */
;/* transfers control to the target independent initialization */
;/* function INC_Initialize. Responsibilities of this function */
;/* include the following: */
;/* */
;/* - Setup necessary processor/system control registers */
;/* - Initialize the vector table */
;/* - Setup the system stack pointers */
;/* - Setup the timer interrupt */
;/* - Calculate the timer HISR stack and priority */
;/* - Calculate the first available memory address */
;/* - Transfer control to INC_Initialize to initialize all of */
;/* the system components. */
;/* */
;/* AUTHOR */
;/* */
;/* Barry Sellew, Accelerated Technology, Inc. */
;/* */
;/* CALLED BY */
;/* */
;/* none */
;/* */
;/* CALLS */
;/* */
;/* INC_Initialize Common initialization */
;/* */
;/* INPUTS */
;/* */
;/* None */
;/* */
;/* OUTPUTS */
;/* */
;/* None */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* B. Sellew 01-19-1996 Created initial version 1.0 */
;/* B. Sellew 01-22-1996 Verified version 1.0 */
;/* */
;/*************************************************************************/
;VOID INT_Initialize(void)
;{
.def _c_int00
_c_int00
.include "init.asm"
.if CHIPSET = 15
addrCS0 .word 0xfffffb04 ; CS0 address space
.else
addrCS0 .word 0xfffffb00 ; CS0 address space
.endif
.if OP_L1_STANDALONE = 0
.if BOARD = 40 | 41
EX_MPU_CONF_REG .word 0xFFFEF006 ; Extended MPU configuration register address
EX_FLASH_VALUE .short 0x0008 ; set bit to enable A22
.endif
.if BOARD = 70 | BOARD = 71
MPU_CONF_GPIO_39_REG .word 0xFFFEF19C ; CONF_GPIO_39 Register
A22_ENABLE_VALUE .short 0x0001
.endif
.endif ; OP_L1_STANDALONE = 0
.if CHIPSET = 4
CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address
CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
; Use DPLL, Divide by 1
.if OP_L1_STANDALONE = 1
DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
.else
DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
.endif
RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register
; independently of the ARM clock
.elseif CHIPSET = 6
CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector
.elseif CHIPSET = 7 | CHIPSET = 8
CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
; Use DPLL, Divide by 1
.if OP_L1_STANDALONE = 1
DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
.else
DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
.endif
DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
.if OP_L1_STANDALONE = 0
ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
.endif
MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
.elseif CHIPSET = 10 | CHIPSET = 11
CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
; Use DPLL, Divide by 1
.if OP_L1_STANDALONE = 1
DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
.else
DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
.endif
DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
.if OP_L1_STANDALONE = 0
ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module
.endif
MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
.elseif CHIPSET = 12
DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address
CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
; Use DPLL, Divide by 1
DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value
.elseif CHIPSET = 15
CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
; Use DPLL, Divide by 1
DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state
DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
.endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12 or 15
c_cinit .long cinit
;OMAPS00058957
.if (TOOL_CHOICE > 1)
c_pinit .long pinit
.endif
;OMAPS00058957 end
.def _INT_Initialize
_INT_Initialize
;
; Configuration of ARM clock and DPLL frequency
;
.if CHIPSET = 4
;
; Configure RHEA access factor in order to allow the access of DPLL register
;
ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1
ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2
strh r2,[r1] ; Store DPLL reset value in RHEA control register
;
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldr r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
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