?? int.s
字號:
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
.elseif CHIPSET = 6
;
; Set VTCXO_26MHZ bit to '1' in case of the VTCXO clock is 26MHz instead
; of 13MHz.
;
ldr r1, CNTL_ARM_CLK_REG ; Load CLKM base register address in R1
ldrh r2, [r1,#2] ; Load contents of CNTL_CLK register in R2
ldr r0, CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector
orr r0, r0, r2;
strh r0, [r1,#2];
.if OP_L1_STANDALONE = 0
; Wait a while until clock is stable (required for AvengerII)
mov r0,#0x100
WaitAWhile1:
sub r0, r0, #1
cmp r0, #0
bne WaitAWhile1
.endif ; OP_L1_STANDALONE = 0
.elseif CHIPSET = 7
;
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldr r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
;
; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
;
ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
.if OP_L1_STANDALONE = 1
ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
orr r0,r0,r2 ; Disable DU module
.else
;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
;orr r0,r0,r2 ; Disable DU module
and r0,r0,r2 ; Enable DU module
.endif ; OP_L1_STANDALONE
strh r0,[r1] ; Store configuration in Extra Control register CONF
;
; Disable all MPU protections
;
ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
strh r2,[r1] ; Store reset value of MPU_CTL register
.elseif CHIPSET = 8
;
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldr r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
;
; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
;
ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
.if OP_L1_STANDALONE = 1
ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
orr r0,r0,r2 ; Disable DU module
.else
;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
;orr r0,r0,r2 ; Disable DU module
and r0,r0,r2 ; Enable DU module
.endif ; OP_L1_STANDALONE
strh r0,[r1] ; Store configuration in Extra Control register CONF
;
; Disable all MPU protections
;
ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
strh r2,[r1] ; Store reset value of MPU_CTL register
.elseif CHIPSET = 10
;
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldr r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
;
; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
;
ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
.if OP_L1_STANDALONE = 1
ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
orr r0,r0,r2 ; Disable DU module
.else
;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
;orr r0,r0,r2 ; Disable DU module
and r0,r0,r2 ; Enable DU module
.endif ; OP_L1_STANDALONE
strh r0,[r1] ; Store configuration in Extra Control register CONF
;
; Disable all MPU protections
;
ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
strh r2,[r1] ; Store reset value of MPU_CTL register
.elseif CHIPSET = 11
;
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldr r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
;
; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
;
ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
.if OP_L1_STANDALONE = 1
ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
orr r0,r0,r2 ; Disable DU module
.else
;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF
ldrh r0,[r1] ; Load Extra Control register CONF in r0
;orr r0,r0,r2 ; Disable DU module
and r0,r0,r2 ; Enable DU module
.endif ; OP_L1_STANDALONE
strh r0,[r1] ; Store configuration in Extra Control register CONF
;
; Disable all MPU protections
;
ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
strh r2,[r1] ; Store reset value of MPU_CTL register
.elseif CHIPSET = 12
.if BOARD = 6
; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4
ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1
ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2
strh r2,[r1] ; Store reset value in register
;
.endif ; BOARD = 6
;
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldr r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
;
; Disable the DU module by setting bit 11 to '1'
;
; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
; ldrh r0,[r1] ; Load Extra Control register CONF in r0
; orr r0,r0,r2 ; Disable DU module
; strh r0,[r1] ; Store configuration in Extra Control register CONF
;
; Disable all MPU protections
;
ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
strh r2,[r1] ; Store reset value of MPU_CTL register
.elseif CHIPSET = 15
; Configure DPLL register with reset value
;
ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
strh r2,[r1] ; Store DPLL reset value in DPLL register
;
; Wait that DPLL goes in BYPASS mode
;
Wait_DPLL_Bypass
ldrh r2,[r1] ; Load DPLL register
and r2,r2,#1 ; Perform a mask on bit 0
cmp r2,#1 ; Compare DPLL lock bit
beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
;
; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
; generate ARM clock with division factor of 1.
;
ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
.if VIRTIO!=1
;
; Disable all MPU protections
;
ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
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