?? int.s
字號:
strh r2,[r1] ; Store reset value of MPU_CTL register
.endif
.endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12 or 15
;
; Wait-state configuration of external and internal memories
;
ldr r1,addrCS0
.if CHIPSET != 12 & CHIPSET != 15
ldrh r2,CS0_MEM_REG ; ROM initialization
strh r2,[r1] ; CS0
ldrh r2,CS1_MEM_REG ; RAM Initialization
strh r2,[r1,#2] ; CS1
ldrh r2,CS2_MEM_REG ; RAM Initialization
strh r2,[r1,#4] ; CS2
.if BOARD != 35
.if BOARD != 46
ldrh r2,CS3_MEM_REG ; Parallel I/O on B-Sample
strh r2,[r1,#6] ; CS3 (unused on EVA4?)
ldrh r2,CS4_MEM_REG ; Latch on B-Sample
strh r2,[r1,#0xa] ; CS4 (unused on EVA4)
.endif
.endif
.elseif CHIPSET = 15
ldr r2,CS0_MEM_REG ; pSRAM initialization
str r2,[r1] ; CS0
ldr r2,CS3_MEM_REG ; NOR flash initialization
str r2,[r1,#0x0C] ; CS3
.else
ldrh r2,CS0_MEM_REG ; FLASH Initialization
strh r2,[r1,#0x0] ; CS0
ldrh r2,CS5_MEM_REG ; FLASH Initialization
strh r2,[r1,#0xA] ; CS5
ldrh r2,CS4_MEM_REG ; RAM Initialization
strh r2,[r1,#0x8] ; CS4
.endif
.if CHIPSET == 3
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
.elseif CHIPSET == 4
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0x8] ; CS7 Internal Boot RAM
.elseif CHIPSET == 5
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
.elseif CHIPSET == 6
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
.elseif CHIPSET == 7
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
.elseif CHIPSET == 8
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
.elseif CHIPSET == 10
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
.if BOARD == 35 | BOARD == 46
mov r2,#API_ADAPT ; API-RHEA configuration
strh r2,[r1,#0xE]
bl Ensure_external_access
bl Copy_code_into_CS7
bl Toggle_nIBoot
bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM
.endif
.elseif CHIPSET == 11
ldrh r2,CS6_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0xc] ; CS6 Internal RAM
ldrh r2,CS7_MEM_REG ; Internal SRAM initialization
strh r2,[r1,#0x8] ; CS7 Internal Boot ROM
.endif
.if OP_L1_STANDALONE = 0
.if BOARD = 40 | BOARD = 41
; /* On D-Sample Board, use A22 mode (ADD(22) instead of CS4) to be able to
; address 8 Mbytes especially with CS0 (Flash) & CS3 (External Peripherals) */
ldr r1,EX_MPU_CONF_REG
ldrh r2,[r1]
ldr r0,EX_FLASH_VALUE
orr r0, r0, r2
strh r0,[r1]
.endif ; BOARD = 40 | 41
.if BOARD = 70 | BOARD = 71
; On I-Sample board A22 must be enabled to access full 128 Mbit Memory
ldr r1,MPU_CONF_GPIO_39_REG
ldrh r2,[r1]
ldr r0,A22_ENABLE_VALUE
strh r0,[r1]
.endif ; BOARD 70 | 71
.endif ; OP_L1_STANDALONE = 0
;
; /* Insure that the processor is in supervisor mode. */
;
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
ORR a1,a1,#LOCKOUT ; Insure IRQ and FIQ interrupts are
; locked out
MSR CPSR,a1 ; Setup the new CPSR
;
; NEW COMPILER MANAGEMENT
; REWORK OF .bss INITIALIZATION - start
; Creation of INT_memset and INT_memcpy, respectively identical to memset and
; memcpy from the rts library of compiler V2.51.
; They are used to make the initialization of the .bss section and the load
; of the internal ram code not dependent to the 32-bit alignment.
; The old code used for the initialization and the load used a loop with
; 4-byte increment, assuming the 32-bit alignment of the .bss section.
; This alignment is not true with compiler V2.51.
; This change applies whatever the compiler version.
;
; /* Clear the un-initialized global and static C data areas. */
; Initialize the system stack pointer a first time to allow use of memset function
; which needs stack.
; The system stack pointers will be fully initialized after having cleared
; the BSS area. */
;
.if OP_L1_STANDALONE = 1
LDR a1,BSS_End ; Pickup the ending address of BSS
; MQ added the following two lines to avoid messing the last few sections.
MOV a2,#OTHER_SECTIONS ; jump over other sections behind
ADD a1,a1,a2 ; BSS_END.
.else
LDR a1,StackSegment ; Pickup the begining address from .cmd file
; (is aligned on 8 byte boundary)
.endif ; OP_L1_STANDALONE
MOV a2,#SYSTEM_SIZE ; Pickup system stack size
SUB a2,a2,#4 ; Subtract one word for first addr
ADD a3,a1,a2 ; Build start of system stack area
.if OP_L1_STANDALONE = 1
BIC a3,a3,#3 ; Insure word aligment of stack
.endif
MOV sp,a3 ; Setup initial stack pointer
.if (OP_L1_STANDALONE=0) & (BOARD=35)
.if (USE_GZIP = 1)
.if LONG_JUMP = 3
BL _f_load_int_mem ; Download FLASH to Internal RAM
.endif ; (LONG_JUMP = 3)
.endif ; (USE_GZIP = 1)
.endif ; (OP_L1_STANDALONE=0) & (BOARD=35)
STMFD sp!,{a1-a4} ; Save a1-a4 registers to stack
LDR a1,BSS_Start ; Pickup the start of the BSS area
LDR a3,BSS_End ; Pickup the end of the BSS area
SUB a3,a3,a1 ; Calculate size of the BSS area
MOV a2,#0 ; Clear value in a2
BL _INT_memset ; Clear the BSS area using memset function
.if LONG_JUMP = 3 ; Visual Linker
LDR a1,BSS_IntMem_Start ; Pickup the start of the BSS area
LDR a3,BSS_IntMem_End ; Pickup the end of the BSS area
SUB a3,a3,a1 ; Calculate size of the BSS area
MOV a2,#0 ; Clear value in a2
BL _INT_memset ; Clear the BSS area using memset function
.endif
LDMFD sp!,{a1-a4} ; Restore a1-a4 registers from stack
; NEW COMPILER MANAGEMENT
; REWORK OF .bss INITIALIZATION - end
;
; /* Setup the vectors loaded flag to indicate to other routines in the
; system whether or not all of the default vectors have been loaded.
; If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the
; default vector to be loaded. In the THUMB this variable is always
; set to 1. All vectors must be setup by this function. */
; INT_Loaded_Flag = 0;
;
MOV a1,#1 ; All vectors are assumed loaded
LDR a2,Loaded_Flag ; Build address of loaded flag
STR a1,[a2,#0] ; Initialize loaded flag
.if (GSM_IDLE_RAM=0) | (BOARD=35 & OP_L1_STANDALONE=0)
;
.if OP_L1_STANDALONE = 1
; /* Initialize the system stack pointers. This is done after the BSS is
; clear because the TCD_System_Stack pointer is a BSS variable! It is
; assumed that available memory starts immediately after the end of the
; BSS section. */
;
LDR a1,BSS_End ; Pickup the ending address of BSS
; MQ added the following two lines to avoid messing the last few sections.
MOV a2,#OTHER_SECTIONS ; jump over other sections behind
ADD a1,a1,a2 ; BSS_END.
.else
; /* Initialize the system stack pointers. This is done after the BSS is
; cleared because the TCD_System_Stack pointer is a BSS variable! It is
; assumed that the .cmd file is written to direct where these stacks should
; be allocated and to align them on double word boundaries.
;
LDR a1,StackSegment ; Pickup the begining address from .cmd file
; (is aligned on 8 byte boundary)
.endif ; OP_L1_STANDALONE
MOV a2,#SYSTEM_SIZE ; Pickup system stack size
SUB a2,a2,#4 ; Subtract one word for first addr
ADD a3,a1,a2 ; Build start of system stack area
.if OP_L1_STANDALONE = 1
BIC a3,a3,#3 ; Insure word aligment of stack
.endif
MOV v7,a1 ; Setup initial stack limit
LDR a4,System_Limit ; Pickup system stack limit address
STR v7,[a4, #0] ; Save stack limit
MOV sp,a3 ; Setup initial stack pointer
LDR a4,System_Stack ; Pickup system stack address
STR sp,[a4, #0] ; Save stack pointer
MOV a2,#IRQ_STACK_SIZE ; Pickup IRQ stack size in bytes
ADD a3,a3,a2 ; Allocate IRQ stack area
.if OP_L1_STANDALONE = 1
BIC a3,a3,#3 ; Insure word alignment
.endif
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits
MSR CPSR,a1 ; Move to IRQ mode
MOV sp,a3 ; Setup IRQ stack pointer
MOV a2,#FIQ_STACK_SIZE ; Pickup FIQ stack size in bytes
ADD a3,a3,a2 ; Allocate FIQ stack area
.if OP_L1_STANDALONE = 1
BIC a3,a3,#3 ; Insure word alignment
.endif
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits
MSR CPSR,a1 ; Move to the FIQ mode
MOV sp,a3 ; Setup FIQ stack pointer
.if OP_L1_STANDALONE = 0
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#ABORT_MODE ; Set the Abort mode bits
MSR CPSR,a1 ; Move to the Abort mode
LDR sp,Exception_Stack ; Setup Abort stack pointer
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#UNDEF_MODE ; Set the Undefined mode bits
MSR CPSR,a1 ; Move to the Undefined mode
LDR sp,Exception_Stack ; Setup Undefined stack pointer
; (should never be used)
.endif
; go to Supervisor Mode
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
MSR CPSR,a1 ; All interrupt stacks are setup,
; return to supervisor mode
;
; /* Define the global data structures that need to be initialized by this
; routine. These structures are used to define the system timer
; management HISR. */
; TMD_HISR_Stack_Ptr = (VOID *) a3;
; TMD_HISR_Stack_Size = TIMER_SIZE;
; TMD_HISR_Priority = TIMER_PRIORITY;
;
; TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
; area. The Timer HISR (called "SYSTEM H") and its related stack will be created
; in TMI_Initialize(). The current stack pointer will be set at the bottom (the
; lowest address) of the expected area.
LDR a4,HISR_Stack_Ptr ; Pickup variable's address
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