?? int.s
字號:
ADD a3,a3,#4 ; Increment to next available word
STR a3,[a4, #0] ; Setup timer HISR stack pointer
MOV a2,#TIMER_SIZE ; Pickup the timer HISR stack size
BIC a2,a2,#3 ; Insure word alignment
ADD a3,a3,a2 ; Allocate the timer HISR stack
; from available memory
LDR a4,HISR_Stack_Size ; Pickup variable's address
STR a2,[a4, #0] ; Setup timer HISR stack size
MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2)
LDR a4,HISR_Priority ; Pickup variable's address
STR a2,[a4, #0] ; Setup timer HISR priority
.elseif (GSM_IDLE_RAM=1) & (OP_L1_STANDALONE=1)
;
; Setup of IRQ stack pointer
;
LDR a1, irq_stack_buf_size ; Get address of variable containing stack size in a1
LDR a1, [a1, #0] ; Get content of variable
SUB a1, a1, #4 ; Substract 4 to get last available address of stack
LDR a2, irq_stack_buf ; Get IRQ stack buffer address in a2
ADD a2, a2, a1 ; Add a1 and a2 to get last address of stack
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits
MSR CPSR,a1 ; Move to IRQ mode
MOV sp,a2 ; Setup IRQ stack pointer
;
; Setup of FIQ stack pointer
;
LDR a1, fiq_stack_buf_size ; Get FIQ stack size in a1
LDR a1, [a1, #0] ; Get content of variable
SUB a1, a1, #4 ; Substract 4 to get last available address of stack
LDR a2, fiq_stack_buf ; Get FIQ stack buffer address in a2
ADD a2, a2, a1 ; Add a1 and a2 to get last address of stack
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear the mode bits
ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits
MSR CPSR,a1 ; Move to FIQ mode
MOV sp,a2 ; Setup FIQ stack pointer
;
; Go back in supervisor mode
;
MRS a1,CPSR ; Pickup current CPSR
BIC a1,a1,#MODE_MASK ; Clear mode bits
ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits
MSR CPSR,a1 ; All interrupt stacks are setup,
; return to supervisor mode
;
; Setup of SVC stack pointer
;
LDR a1, svc_stack_buf_size ; Get address of variable containing stack size in a1
LDR a1, [a1, #0] ; Get content of variable
SUB a1, a1, #4 ; Substract 4 to get last available address of stack
LDR a2, svc_stack_buf ; Get SVC stack buffer address in a2
ADD a2, a2, a1 ; Add a1 and a2 to get last address of stack
MOV sp,a2 ; Setup SVC stack pointer
LDR a2, svc_stack_buf ; Get SVC stack buffer address in a2
LDR a4,System_Limit ; Pickup system stack limit address
STR a2,[a4, #0] ; Save stack limit
LDR a4,System_Stack ; Pickup system stack address
STR sp,[a4, #0] ; Save stack pointer
;
; Setup of HISR TIMER stack pointer
;
LDR a4,HISR_Stack_Ptr ; Pickup variable's address
LDR a2,timer_hisr_stack_buf ; Pickup variable's address
STR a2,[a4, #0] ; Setup timer HISR stack pointer
LDR a4,HISR_Stack_Size ; Pickup variable's address
LDR a2,timer_hisr_stack_buf_size ; Pickup variable's address
LDR a2, [a2, #0]
STR a2,[a4, #0] ; Setup timer HISR stack size
MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2)
LDR a4,HISR_Priority ; Pickup variable's address
STR a2,[a4, #0] ; Setup timer HISR priority
.endif ; GSM_IDLE_RAM
.if CHIPSET = 12 | CHIPSET == 15
; This sequence must be always done in order to download the interrupt
; vector remapping
MOV V1, a3 ; Save a3 register
BL _f_load_int_mem ; Download FLASH to Internal RAM
MOV a3, V1 ; Restore a3 register
.else
.if LONG_JUMP = 3
.if (OP_L1_STANDALONE=0) & (BOARD=35)
.if (USE_GZIP = 0) ; Note: f_load_int_mem already done for (OP_L1_STANDALONE=0 & BOARD=35 & USE_GZIP=1)
MOV V1, a3 ; Save a3 register
BL _f_load_int_mem ; Download FLASH to Internal RAM
MOV a3, V1 ; Restore a3 register
.endif ; (USE_GZIP = 0)
.else
MOV V1, a3 ; Save a3 register
BL _f_load_int_mem ; Download FLASH to Internal RAM
MOV a3, V1 ; Restore a3 register
.endif ; !((OP_L1_STANDALONE=0) & (BOARD=35))
.endif ; (LONG_JUMP = 3)
.endif ; CHIPSET != 12 | CHIPSET != 15
.if OP_L1_STANDALONE = 0
; We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
; checking the status of the stacks later.
; inputs:
; a3 still has the bottom of all four stacks and is aligned.
; algorithm:
; We start from the top of all four stacks (*System_Limit), which is
; necessarily aligned. We store 0xFEFEFEFE until we have filled the
; bottom of the fourth stack
; outputs:
; memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
; a3 still has the bottom of all four stacks
LDR a2,System_Limit ; pickup system stack limit address
LDR a1,[a2] ; a1 = StackSegment
MOV a4,#0FEh ; use this and the next 7 instructons to set a4 = 0xFEFEFEFE
STRB a4,[a1, #0]
STRB a4,[a1, #1]
STRB a4,[a1, #2]
STRB a4,[a1, #3]
LDR a4,[a1],#4 ; stored first word, move to second
fill_stack:
STR a4,[a1],#4 ; store a word and increment by four
CMP a1,a3 ; is this the last address?
BLT fill_stack ; if not, loop back
.endif ; OP_L1_STANDALONE = 0
;
; Perform auto-initialization. if cinit is -1, then there is none.
; ------- OP_L1_STANDALONE = 1
; Do not modify a3 (r2) which points to first_available_memory
; ------- OP_L1_STANDALONE = 1
;
LDR r0, c_cinit
CMN r0, #1
BLNE _auto_init
;OMAPS00058957
.if (TOOL_CHOICE > 1)
;*------------------------------------------------------
;* CALL INITIALIZATION ROUTINES FOR CONSTRUCTORS. IF
;* PINIT IS -1, THEN THERE ARE NONE.
;*------------------------------------------------------
LDR r5, c_pinit
CMN r5, #1
BEQ _application_
B _c1_
_loop_: BL IND_CALL
_c1_: LDR r4, [r5], #4
CMP r4, #0
BNE _loop_
_application_:
.endif
; OMAPS00058957 end
;
; /* Call INC_Initialize with a pointer to the first available memory
; address after the compiler's global data. This memory may be used
; by the application. */
; INC_Initialize(first_available_memory);
;
MOV a1,a3 ; Pass the first available memory
B _INC_Initialize ; to high-level initialization
;}
;
.if BOARD=35 | BOARD=46
;/*
; * FUNCTION
; *
; * Ensure_external_access
; */
Ensure_external_access:
;AI_ResetBit(4); // request shared mem clock
ldr r1, armio_out
ldrh r2, [r1]
bic r2, r2, #0x10
strh r2, [r1]
;while(AI_ReadBit(5)!=1); // wait for acknowledge
ack:
ldr r1, armio_in
ldrh r2, [r1]
and r2, r2, #0x20
cmp r2, #0x20
bne ack
bx lr ; Return to caller
;/*
; * FUNCTION
; *
; * Copy_code_into_CS7
; */
Copy_code_into_CS7:
ldr r1, addrExtraConf
ldr r3, DEF_EXTRA_CONF
strh r3, [r1] ; ensure CS7 selects internal memory
mov r0, #CS7_SIZE ; size of CS7 memory in bytes
mov r1, #CS7_ADDR ; destination
mov r2, #0 ; source
CopyIntCode:
ldr r3,[r2]
str r3,[r1]
add r1, r1, #4
add r2, r2, #4
sub r0, r0, #4
cmp r0, #0
bne CopyIntCode
ldr r1, addrCS7
ldr r2, [r1]
bic r2, r2, #0x80 ; Write Enable OFF on CS7
strh r2, [r1]
bx lr ; Return to caller
;/*
; * FUNCTION
; *
; * Toggle_nIBoot
; */
Toggle_nIBoot:
ldr r1, addrExtraConf ; Address of Extra Conf Register
ldr r3, EXTRA_CONF ; set CS7 at address zero
strh r3, [r1]
bx lr ; Return to caller
;/*
; * FUNCTION
; *
; * Clear_Internal_SRAM
; */
Clear_Internal_SRAM:
mov r0, #SRAM_ADDR ; r0 points to SRAM start
mov r1, #SRAM_SIZE
add r1, r0, r1 ; r1 points to SRAM end
mov r2, #0
ClearSram:
str r2,[r0], #4
cmp r0, r1 ; done?
bne ClearSram ; no - loop
bx lr ; Return to caller
.endif ; BOARD = 35, 46
;
;/*************************************************************************/
;/* */
;/* FUNCTION */
;/* */
;/* INT_Vectors_Loaded */
;/* */
;/* DESCRIPTION */
;/* */
;/* This function returns the flag that indicates whether or not */
;/* all the default vectors have been loaded. If it is false, */
;/* each LISR register also loads the ISR shell into the actual */
;/* vector table. */
;/* */
;/* AUTHOR */
;/* */
;/* Barry Sellew, Accelerated Technology, Inc. */
;/* */
;/* CALLED BY */
;/* */
;/* TCC_Register_LISR Register LISR for vector */
;/* */
;/* CALLS */
;/* */
;/* None */
;/* */
;/* INPUTS */
;/* */
;/* None */
;/* */
;/* OUTPUTS */
;/* */
;/* None */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* B. Sellew 01-19-1996 Created initial version 1.0 */
;/* B. Sellew 01-22-1996 Verified version 1.0 */
;/* */
;/*************************************************************************/
;INT INT_Vectors_Loaded(void)
;{
.def $INT_Vectors_Loaded
$INT_Vectors_Loaded ; Dual-state interworking?? 快捷鍵說明
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