?? dynamic_clock_12.h
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/************* Revision Controle System Header *************
* GSM Layer 1 software
* DYNAMIC_CLOCK_12_H
*
* Filename dynamic_clock_12.h
* Copyright 2003 (C) Texas Instruments
*
************* Revision Controle System Header *************/
/***********************************************************************************************
* Only SAMSON/CALYPSO families are considered for dynamic clock configuration.
***********************************************************************************************
*
* CHIPSET = 12 (CALYPSO PLUS C035)
*
***********************************************************************************************
* Supported clock configuration
*
*
* CHIPSET 78/78/13 78/78/39 104/104/52 156/78/52 130/130/65
* (0) (1) (2) (3) (4)
*
* CALYPSO PLUS c035 (12) NA X X X X
*
*
*
* BOARD CHIPSET Access Time (ns)
* CS0 CS1 CS2 CS3 CS4 CS5
*
* EVA4 (RAM) (6) CALYPSO PLUS 100 NA NA NA 100 100
* E-Sample (SRAM) (42) CALYPSO PLUS NA NA NA NA 70 70
* E-Sample (FLASH) (43) CALYPSO PLUS NA NA NA NA 70 70
*
***********************************************************************************************/
#include "chipset.cfg"
#include "board.cfg"
#if (CHIPSET == 12)
#ifndef _DYNAMIC_CLOCK_12_H_
#define _DYNAMIC_CLOCK_12_H_
#ifdef _DYNAMIC_CLOCK_C_
/***************************************************************************
* C_CLOCK_CFG_78_78_13 configuration
**************************************************************************/
/* Not applicable due to API 16-bits read problem */
/***************************************************************************
* C_CLOCK_CFG_78_78_39 configuration
**************************************************************************/
const T_DYNAMIC_CLOCK_CFG d_12_78_78_39_clock =
{
/* Index of the present clock configuration */
C_CLOCK_CFG_78_78_39,
/* DSP clock in kHz */
78000,
/* DPLL configuration */
DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 6,
/* ARM clock configuration */
CLKM_SEL_DPLL, 2, CLKM_DISABLE_XP5,
/* DSP configuration */
CLKM_DSP_DIV_1,
/* DSP latencies configuration */
D_LAT_MCU_HOM2SAM,
D_LAT_MCU_BRIDGE,
D_LAT_MCU_BEF_FAST_ACCESS,
D_LAT_DSP_AFTER_SAM,
D_TRANSFER_RATE,
/* API-RHEA configuration */
/* API_WS */
1, 1,
// 1 WS in HOM mode to workaround HW bug 3504
// dma_arbtrs > Concurrent access to API from DMA and MCU
/* RHEA Access Factor */
// should be 0xFE00 due to no DMA limitation at 34MHz
// Must be updated according to ARM clock configuration
// Timeout must be set to 0xFF for chipset
// Calypso C035 at 52MHz
0, 0,
/* RHEA Timeout */
0xFF,
/* EMIF configuration */
/* structure used for CHIPSET 12 is different, see definition in sys_memif.h */
/* new memif drivers integrate new features as Page mode */
#if (BOARD == 6)
// CS0
{
/* CONF_CS0 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4
{
/* CONF_CS4 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5
{
/* CONF_CS5 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 6
#elif (BOARD == 42) // E-Sample SRAM
// CS0
{
/* CONF_CS0 register configuration */
3,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - FLASH
{
/* CONF_CS4 register configuration */
3,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - External SRAM
{
/* CONF_CS5 register configuration */
3,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 42
#elif (BOARD == 43) // E-Sample FLASH
// CS0
{
/* CONF_CS0 register configuration */
3,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - External SRAM
{
/* CONF_CS4 register configuration */
3,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - FLASH
{
/* CONF_CS5 register configuration */
3,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_EN,C_MEMIF_PMS_16B,1,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 43
#elif (BOARD == 45) // EVA-Conso FLASH
// Not validated
// CS0
{
/* CONF_CS0 register configuration */
6,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS0 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS0 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS4 - External SRAM
{
/* CONF_CS4 register configuration */
5,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS4 register configuration */
C_MEMIF_PAGE_MODE_DIS,C_MEMIF_PMS_4B,15,15,
/* DCCTRL_CS4 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// CS5 - FLASH
{
/* CONF_CS5 register configuration */
4,C_MEMIF_DVS_16,C_MEMIF_WRITE_EN,0,C_MEMIF_RODC_DIS,C_MEMIF_WRDC_DIS,C_MEMIF_WWS_VALUE_EN,
/* EXWS_CS5 register configuration */
C_MEMIF_PAGE_MODE_EN,C_MEMIF_PMS_16B,2,15,
/* DCCTRL_CS5 register configuration */
C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS,C_MEMIF_DCECS_DIS
},
// BOARD == 45
#else
#error "This BOARD configuration is not supported"
#endif
};
/***************************************************************************
* C_CLOCK_CFG_104_104_52 configuration
**************************************************************************/
const T_DYNAMIC_CLOCK_CFG d_12_104_104_52_clock =
{
/* Index of the present clock configuration */
C_CLOCK_CFG_104_104_52,
/* DSP clock in kHz */
104000,
/* DPLL configuration */
DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 8,
/* ARM clock configuration */
CLKM_SEL_DPLL, 2, CLKM_DISABLE_XP5,
/* DSP configuration */
CLKM_DSP_DIV_1,
/* DSP latencies configuration */
D_LAT_MCU_HOM2SAM,
D_LAT_MCU_BRIDGE,
D_LAT_MCU_BEF_FAST_ACCESS,
D_LAT_DSP_AFTER_SAM,
D_TRANSFER_RATE,
/* API-RHEA configuration */
/* API_WS */
1, 1,
// 1 WS in HOM mode to workaround HW bug 3504
// dma_arbtrs > Concurrent access to API from DMA and MCU
/* RHEA Access Factor */
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