?? data_drive.tan.qmsg
字號:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk_SCL " "Info: Assuming node \"Clk_SCL\" is an undefined clock" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clk_SCL" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk_SCL register cnt1\[1\] register cnt1\[5\] 227.27 MHz 4.4 ns Internal " "Info: Clock \"Clk_SCL\" has Internal fmax of 227.27 MHz between source register \"cnt1\[1\]\" and destination register \"cnt1\[5\]\" (period= 4.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt1\[1\] 1 REG LC1_A2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A2; Fanout = 4; REG Node = 'cnt1\[1\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { cnt1[1] } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.400 ns) 0.800 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC3_A1 2 " "Info: 2: + IC(0.400 ns) + CELL(0.400 ns) = 0.800 ns; Loc. = LC3_A1; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.800 ns" { cnt1[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.900 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC4_A1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 0.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.100 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC5_A1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 1.000 ns; Loc. = LC5_A1; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.100 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.100 ns lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC6_A1 1 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 1.100 ns; Loc. = LC6_A1; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.100 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 2.000 ns lpm_add_sub:add_rtl_0\|addcore:adder\|unreg_res_node\[5\] 6 COMB LC7_A1 1 " "Info: 6: + IC(0.000 ns) + CELL(0.900 ns) = 2.000 ns; Loc. = LC7_A1; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_0\|addcore:adder\|unreg_res_node\[5\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.900 ns" { lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/addcore.tdf" 95 16 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.800 ns) 3.200 ns cnt1~12 7 COMB LC6_A2 1 " "Info: 7: + IC(0.400 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC6_A2; Fanout = 1; COMB Node = 'cnt1~12'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.200 ns" { lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5] cnt1~12 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.400 ns) 3.700 ns cnt1\[5\] 8 REG LC2_A2 4 " "Info: 8: + IC(0.100 ns) + CELL(0.400 ns) = 3.700 ns; Loc. = LC2_A2; Fanout = 4; REG Node = 'cnt1\[5\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.500 ns" { cnt1~12 cnt1[5] } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 75.68 % " "Info: Total cell delay = 2.800 ns ( 75.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns 24.32 % " "Info: Total interconnect delay = 0.900 ns ( 24.32 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "3.700 ns" { cnt1[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5] cnt1~12 cnt1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { cnt1[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5] cnt1~12 cnt1[5] } { 0.000ns 0.400ns 0.000ns 0.000ns 0.000ns 0.000ns 0.400ns 0.100ns } { 0.000ns 0.400ns 0.100ns 0.100ns 0.100ns 0.900ns 0.800ns 0.400ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns cnt1\[5\] 2 REG LC2_A2 4 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_A2; Fanout = 4; REG Node = 'cnt1\[5\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.200 ns" { Clk_SCL cnt1[5] } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL cnt1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out cnt1[5] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"Clk_SCL\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns cnt1\[1\] 2 REG LC1_A2 4 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1_A2; Fanout = 4; REG Node = 'cnt1\[1\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.200 ns" { Clk_SCL cnt1[1] } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL cnt1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out cnt1[1] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL cnt1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out cnt1[5] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL cnt1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out cnt1[1] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "3.700 ns" { cnt1[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5] cnt1~12 cnt1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { cnt1[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5] cnt1~12 cnt1[5] } { 0.000ns 0.400ns 0.000ns 0.000ns 0.000ns 0.000ns 0.400ns 0.100ns } { 0.000ns 0.400ns 0.100ns 0.100ns 0.100ns 0.900ns 0.800ns 0.400ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL cnt1[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out cnt1[5] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL cnt1[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out cnt1[1] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "Adc_Conv~reg0 En Clk_SCL 2.900 ns register " "Info: tsu for register \"Adc_Conv~reg0\" (data pin = \"En\", clock pin = \"Clk_SCL\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest pin register " "Info: + Longest pin to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns En 1 PIN PIN_89 2 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 2; PIN Node = 'En'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { En } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns Adc_SCL_Select~15 2 COMB LC1_A5 1 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'Adc_SCL_Select~15'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.000 ns" { En Adc_SCL_Select~15 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 3.200 ns Adc_Conv~128 3 COMB LC2_A5 1 " "Info: 3: + IC(0.100 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC2_A5; Fanout = 1; COMB Node = 'Adc_Conv~128'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.900 ns" { Adc_SCL_Select~15 Adc_Conv~128 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.700 ns) 4.000 ns Adc_Conv~reg0 4 REG LC3_A5 2 " "Info: 4: + IC(0.100 ns) + CELL(0.700 ns) = 4.000 ns; Loc. = LC3_A5; Fanout = 2; REG Node = 'Adc_Conv~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.800 ns" { Adc_Conv~128 Adc_Conv~reg0 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 95.00 % " "Info: Total cell delay = 3.800 ns ( 95.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 5.00 % " "Info: Total interconnect delay = 0.200 ns ( 5.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "4.000 ns" { En Adc_SCL_Select~15 Adc_Conv~128 Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { En En~out Adc_SCL_Select~15 Adc_Conv~128 Adc_Conv~reg0 } { 0.000ns 0.000ns 0.000ns 0.100ns 0.100ns } { 0.000ns 1.300ns 1.000ns 0.800ns 0.700ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Adc_Conv~reg0 2 REG LC3_A5 2 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC3_A5; Fanout = 2; REG Node = 'Adc_Conv~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.200 ns" { Clk_SCL Adc_Conv~reg0 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Adc_Conv~reg0 } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "4.000 ns" { En Adc_SCL_Select~15 Adc_Conv~128 Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { En En~out Adc_SCL_Select~15 Adc_Conv~128 Adc_Conv~reg0 } { 0.000ns 0.000ns 0.000ns 0.100ns 0.100ns } { 0.000ns 1.300ns 1.000ns 0.800ns 0.700ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Adc_Conv~reg0 } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0}
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -