?? data_drive.tan.qmsg
字號:
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk_SCL Adc_SCL Adc_SCL_Select 7.300 ns register " "Info: tco from clock \"Clk_SCL\" to destination pin \"Adc_SCL\" through register \"Adc_SCL_Select\" is 7.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"Clk_SCL\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Adc_SCL_Select 2 REG LC4_A2 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_A2; Fanout = 1; REG Node = 'Adc_SCL_Select'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.200 ns" { Clk_SCL Adc_SCL_Select } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL Adc_SCL_Select } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Adc_SCL_Select } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns + Longest register pin " "Info: + Longest register to pin delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Adc_SCL_Select 1 REG LC4_A2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A2; Fanout = 1; REG Node = 'Adc_SCL_Select'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Adc_SCL_Select } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 1.100 ns Adc_SCL~0 2 COMB LC7_A2 1 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 1.100 ns; Loc. = LC7_A2; Fanout = 1; COMB Node = 'Adc_SCL~0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.100 ns" { Adc_SCL_Select Adc_SCL~0 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(3.800 ns) 5.500 ns Adc_SCL 3 PIN PIN_68 0 " "Info: 3: + IC(0.600 ns) + CELL(3.800 ns) = 5.500 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'Adc_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "4.400 ns" { Adc_SCL~0 Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns 87.27 % " "Info: Total cell delay = 4.800 ns ( 87.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns 12.73 % " "Info: Total interconnect delay = 0.700 ns ( 12.73 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "5.500 ns" { Adc_SCL_Select Adc_SCL~0 Adc_SCL } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.500 ns" { Adc_SCL_Select Adc_SCL~0 Adc_SCL } { 0.000ns 0.100ns 0.600ns } { 0.000ns 1.000ns 3.800ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL Adc_SCL_Select } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Adc_SCL_Select } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "5.500 ns" { Adc_SCL_Select Adc_SCL~0 Adc_SCL } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.500 ns" { Adc_SCL_Select Adc_SCL~0 Adc_SCL } { 0.000ns 0.100ns 0.600ns } { 0.000ns 1.000ns 3.800ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Clk_SCL Adc_SCL 6.500 ns Longest " "Info: Longest tpd from source pin \"Clk_SCL\" to destination pin \"Adc_SCL\" is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.100 ns Adc_SCL~0 2 COMB LC7_A2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.100 ns; Loc. = LC7_A2; Fanout = 1; COMB Node = 'Adc_SCL~0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.800 ns" { Clk_SCL Adc_SCL~0 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(3.800 ns) 6.500 ns Adc_SCL 3 PIN PIN_68 0 " "Info: 3: + IC(0.600 ns) + CELL(3.800 ns) = 6.500 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'Adc_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "4.400 ns" { Adc_SCL~0 Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns 90.77 % " "Info: Total cell delay = 5.900 ns ( 90.77 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 9.23 % " "Info: Total interconnect delay = 0.600 ns ( 9.23 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "6.500 ns" { Clk_SCL Adc_SCL~0 Adc_SCL } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.500 ns" { Clk_SCL Clk_SCL~out Adc_SCL~0 Adc_SCL } { 0.000ns 0.000ns 0.000ns 0.600ns } { 0.000ns 1.300ns 0.800ns 3.800ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "Adc_Conv~reg0 SampleCtrl_in Clk_SCL 0.500 ns register " "Info: th for register \"Adc_Conv~reg0\" (data pin = \"SampleCtrl_in\", clock pin = \"Clk_SCL\") is 0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"Clk_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Adc_Conv~reg0 2 REG LC3_A5 2 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC3_A5; Fanout = 2; REG Node = 'Adc_Conv~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.200 ns" { Clk_SCL Adc_Conv~reg0 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Adc_Conv~reg0 } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns SampleCtrl_in 1 PIN PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 3; PIN Node = 'SampleCtrl_in'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "" { SampleCtrl_in } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 1.700 ns Adc_Conv~reg0 2 REG LC3_A5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 1.700 ns; Loc. = LC3_A5; Fanout = 2; REG Node = 'Adc_Conv~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "0.400 ns" { SampleCtrl_in Adc_Conv~reg0 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 100.00 % " "Info: Total cell delay = 1.700 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.700 ns" { SampleCtrl_in Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.700 ns" { SampleCtrl_in SampleCtrl_in~out Adc_Conv~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.400ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.500 ns" { Clk_SCL Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Adc_Conv~reg0 } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive_cmp.qrpt" Compiler "Data_drive" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/db/Data_drive.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_drive/" "" "1.700 ns" { SampleCtrl_in Adc_Conv~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.700 ns" { SampleCtrl_in SampleCtrl_in~out Adc_Conv~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.400ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 03 18:12:54 2006 " "Info: Processing ended: Thu Aug 03 18:12:54 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0} } { } 0}
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