?? learnning.asm
字號:
; 78K/0S Series C Compiler V1.50 Assembler Source
; Date: 9 Mar 2007 Time:10:28:27
; Command : -flearnning.pcc
; In-file : learnning.c
; Asm-file : learnning.asm
; Para-file : -cF9202
; -yC:\NECTOOLS32\DEV\
; -a
; -zp
; learnning.c
$PROCESSOR(F9202)
$DEBUG
$NODEBUGA
$KANJICODE SJIS
$TOL_INF 03FH, 0150H, 00H, 00H
$DGS FIL_NAM, .file, 01FH, 0FFFEH, 03FH, 067H, 01H, 00H
$DGS AUX_FIL, learnning.c
$DGS MOD_NAM, learnnin, 00H, 0FFFEH, 00H, 077H, 00H, 00H
$DGS SEC_NAM, @@BITS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CNST, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@R_INIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INIT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATA, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@R_INIS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@INIS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@DATS, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CALT, U, U, 00H, 078H, 00H, 00H
$DGS SEC_NAM, @@CODE, U, U, 00H, 078H, 00H, 00H
$DGS GLV_SYM, _learning, U, U, 08001H, 020H, 01H, 02H
$DGS AUX_FUN, 00H, U, U, 01FH, 00H
$DGS BEG_FUN, ??bf_learning, U, U, 00H, 065H, 01H, 00H
$DGS AUX_BEG, 020H, 02H, 011H
$DGS BEG_BLK, ??bb00_learning, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 0CH, 00H, 013H
$DGS BEG_BLK, ??bb01_learning, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 014H, 00H, 015H
$DGS BEG_BLK, ??bb02_learning, U, U, 00H, 064H, 01H, 00H
$DGS AUX_BEG, 01EH, 00H, 00H
$DGS END_BLK, ??eb02_learning, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 022H
$DGS END_BLK, ??eb01_learning, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 023H
$DGS END_BLK, ??eb00_learning, U, U, 00H, 064H, 01H, 00H
$DGS AUX_END, 024H
$DGS END_FUN, ??ef_learning, U, U, 00H, 065H, 01H, 00H
$DGS AUX_END, 025H
$DGS GLV_SYM, _bit_current1, U, U, 0EH, 020H, 00H, 00H
$DGS GLV_SYM, _bit_current2, U, U, 0EH, 020H, 00H, 00H
$DGS GLV_SYM, _delay, U, U, 08001H, 02H, 00H, 02H
$DGS GLV_SYM, _current_check_start, U, U, 034CH, 02H, 00H, 00H
$DGS GLV_SYM, _U1, U, U, 0500CH, 02H, 00H, 00H
$DGS GLV_SYM, _AD_convert, U, U, 08001H, 02H, 00H, 02H
$DGS GLV_SYM, _U2, U, U, 0500CH, 02H, 00H, 00H
$DGS GLV_SYM, _ADCR_U1, U, U, 0EH, 02H, 00H, 00H
$DGS GLV_SYM, @@deilo, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _ADCR_U2, U, U, 0EH, 02H, 00H, 00H
$DGS GLV_SYM, @@hlisub, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _@RTARG0, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _@RTARG1, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, @@iudiv, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, @@deist, U, U, 00H, 02H, 00H, 00H
$DGS GLV_SYM, _bit_current, U, U, 0EH, 02H, 00H, 00H
$DGS GLV_SYM, _battery_U1, U, U, 0EH, 02H, 00H, 00H
$DGS GLV_SYM, _bit_voltage, U, U, 0EH, 02H, 00H, 00H
$DGS GLV_SYM, _programming, U, U, 08001H, 02H, 00H, 02H
EXTRN _delay
EXTRN _U1
EXTRN _AD_convert
EXTRN _U2
EXTRN _ADCR_U1
EXTRN @@deilo
EXTRN _ADCR_U2
EXTRN @@hlisub
EXTRN _@RTARG0
EXTRN _@RTARG1
EXTRN @@iudiv
EXTRN @@deist
EXTRN _bit_current
EXTRN _battery_U1
EXTRN _bit_voltage
EXTRN _programming
EXTBIT _current_check_start
PUBLIC _bit_current1
PUBLIC _bit_current2
PUBLIC _learning
@@BITS BSEG
@@CNST CSEG
@@R_INIT CSEG
@@INIT DSEG
@@DATA DSEG
_bit_current1: DS (2)
_bit_current2: DS (2)
@@R_INIS CSEG UNITP
@@INIS DSEG SADDRP
@@DATS DSEG SADDRP
@@CALT CSEG CALLT0
; line 16
; line 17
; line 18
; line 21
; line 22
; line 23
; line 24
; line 25
; line 26
; line 27
; line 28
; line 29
; line 32
@@CODE CSEG
_learning:
$DGL 1,13
push hl ;[INF] 1, 4
??bf_learning:
; line 34
$DGL 0,3
set1 P4.3 ;[INF] 3, 6
; line 35
$DGL 0,4
movw ax,#02710H ; 10000 ;[INF] 3, 6
call !_delay ;[INF] 3, 6
; line 36
$DGL 0,5
set1 _current_check_start ;[INF] 3, 6
; line 38
$DGL 0,7
mov a,!_U1 ;[INF] 3, 8
xch a,x ;[INF] 1, 4
xor a,a ;[INF] 2, 4
call !_AD_convert ;[INF] 3, 6
; line 39
$DGL 0,8
mov a,!_U2 ;[INF] 3, 8
xch a,x ;[INF] 1, 4
xor a,a ;[INF] 2, 4
call !_AD_convert ;[INF] 3, 6
; line 40
$DGL 0,9
movw de,#_ADCR_U1 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
movw hl,#_ADCR_U2 ;[INF] 3, 6
callt [@@hlisub] ;[INF] 1, 8
mov _@RTARG0,#058H ; 88 ;[INF] 3, 6
mov _@RTARG1,#01BH ; 27 ;[INF] 3, 6
call !@@iudiv ;[INF] 3, 6
movw de,#_bit_current1 ;[INF] 3, 6
callt [@@deist] ;[INF] 1, 8
; line 42
$DGL 0,11
movw de,#_ADCR_U1 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
callt [@@hlisub] ;[INF] 1, 8
cmpw ax,#078H ; 120 ;[INF] 3, 6
bc $$+4 ;[INF] 2, 6
bnz $$+5 ;[INF] 2, 6
br !?L0007 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
callt [@@hlisub] ;[INF] 1, 8
cmpw ax,#0A0H ; 160 ;[INF] 3, 6
bc $$+5 ;[INF] 2, 6
br !?L0007 ;[INF] 3, 6
; line 43
$DGL 0,12
??bb00_learning:
; line 44
$DGL 0,13
movw ax,#0AH ; 10 ;[INF] 3, 6
call !_delay ;[INF] 3, 6
; line 46
$DGL 0,15
mov a,!_U1 ;[INF] 3, 8
xch a,x ;[INF] 1, 4
xor a,a ;[INF] 2, 4
call !_AD_convert ;[INF] 3, 6
; line 47
$DGL 0,16
mov a,!_U2 ;[INF] 3, 8
xch a,x ;[INF] 1, 4
xor a,a ;[INF] 2, 4
call !_AD_convert ;[INF] 3, 6
; line 48
$DGL 0,17
movw de,#_ADCR_U1 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
movw hl,#_ADCR_U2 ;[INF] 3, 6
callt [@@hlisub] ;[INF] 1, 8
mov _@RTARG0,#058H ; 88 ;[INF] 3, 6
mov _@RTARG1,#01BH ; 27 ;[INF] 3, 6
call !@@iudiv ;[INF] 3, 6
movw de,#_bit_current2 ;[INF] 3, 6
callt [@@deist] ;[INF] 1, 8
; line 50
$DGL 0,19
movw de,#_ADCR_U1 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
callt [@@hlisub] ;[INF] 1, 8
cmpw ax,#078H ; 120 ;[INF] 3, 6
bc $?L0007 ;[INF] 2, 6
bz $?L0007 ;[INF] 2, 6
callt [@@deilo] ;[INF] 1, 8
callt [@@hlisub] ;[INF] 1, 8
cmpw ax,#0A0H ; 160 ;[INF] 3, 6
bnc $?L0007 ;[INF] 2, 6
; line 51
$DGL 0,20
??bb01_learning:
; line 52
$DGL 0,21
movw de,#_bit_current1 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
clr1 CY ;[INF] 1, 2
rorc a,1 ;[INF] 1, 2
xch a,x ;[INF] 1, 4
rorc a,1 ;[INF] 1, 2
xch a,x ;[INF] 1, 4
movw bc,ax ;[INF] 1, 4
movw de,#_bit_current2 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
clr1 CY ;[INF] 1, 2
rorc a,1 ;[INF] 1, 2
xch a,x ;[INF] 1, 4
rorc a,1 ;[INF] 1, 2
add a,c ;[INF] 2, 4
xch a,x ;[INF] 1, 4
addc a,b ;[INF] 2, 4
movw de,#_bit_current ;[INF] 3, 6
callt [@@deist] ;[INF] 1, 8
; line 54
$DGL 0,23
clr1 _current_check_start ;[INF] 3, 6
; line 55
$DGL 0,24
clr1 P4.3 ;[INF] 3, 6
; line 56
$DGL 0,25
movw ax,#01388H ; 5000 ;[INF] 3, 6
call !_delay ;[INF] 3, 6
; line 57
$DGL 0,26
set1 P4.0 ;[INF] 3, 6
; line 58
$DGL 0,27
movw ax,#02710H ; 10000 ;[INF] 3, 6
call !_delay ;[INF] 3, 6
; line 59
$DGL 0,28
mov a,!_U1 ;[INF] 3, 8
xch a,x ;[INF] 1, 4
xor a,a ;[INF] 2, 4
call !_AD_convert ;[INF] 3, 6
; line 60
$DGL 0,29
movw de,#_battery_U1 ;[INF] 3, 6
callt [@@deilo] ;[INF] 1, 8
cmpw ax,#014AH ; 330 ;[INF] 3, 6
bc $?L0007 ;[INF] 2, 6
bz $?L0007 ;[INF] 2, 6
cmpw ax,#0177H ; 375 ;[INF] 3, 6
bnc $?L0007 ;[INF] 2, 6
; line 61
$DGL 0,30
??bb02_learning:
; line 62
$DGL 0,31
movw ax,#0389AH ; 14490 ;[INF] 3, 6
movw _@RTARG0,ax ;[INF] 2, 8
callt [@@deilo] ;[INF] 1, 8
call !@@iudiv ;[INF] 3, 6
movw de,#_bit_voltage ;[INF] 3, 6
callt [@@deist] ;[INF] 1, 8
; line 63
$DGL 0,32
clr1 P4.0 ;[INF] 3, 6
; line 64
$DGL 0,33
call !_programming ;[INF] 3, 6
??eb02_learning:
?L0007:
??eb01_learning:
??eb00_learning:
; line 68
$DGL 0,37
??ef_learning:
pop hl ;[INF] 1, 6
ret ;[INF] 1, 6
??ee_learning:
END
; *** Code Information ***
;
; $FILE E:\my_project\compex_charger\v1.52\V1.52_WDT\learnning.c
;
; $FUNC learning(32)
; void=(void)
; CODE SIZE= 235 bytes, CLOCK_SIZE= 652 clocks, STACK_SIZE= 4 bytes
;
; $CALL delay(35)
; void=(unsigned int:ax)
;
; $CALL AD_convert(38)
; void=(int:ax)
;
; $CALL AD_convert(39)
; void=(int:ax)
;
; $CALL delay(44)
; void=(unsigned int:ax)
;
; $CALL AD_convert(46)
; void=(int:ax)
;
; $CALL AD_convert(47)
; void=(int:ax)
;
; $CALL delay(56)
; void=(unsigned int:ax)
;
; $CALL delay(58)
; void=(unsigned int:ax)
;
; $CALL AD_convert(59)
; void=(int:ax)
;
; $CALL programming(64)
; void=(void)
; Target chip : uPD78F9202
; Device file : V3.00
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