/* 8260pc.h - Motorola MPC8260 processor header *//*modification history--------------------Dec 15, 2000 SJZHU created it.Oct 24, 2001 modified by shirley*//*This file contains I/O addresses and related constants for theMotorola MPC8260 processor card. */#ifndef	INCads8260h#define	INCads8260h#include "drv/mem/memDev.h"#include "drv/intrCtl/m8260IntrCtl.h"#define BUS	0				/* bus-less board */#define CPU	PPCEC603			/* CPU type *//* 8260pc *//*#define N_SIO_CHANNELS	 	2		*/ /* No. serial I/O channels */#define N_SIO_CHANNELS	 	1		#define FREQ_40_MHZ		40000000	/* 40 Mhz */#define FREQ_66_MHZ		66000000	/* 66 Mhz */#define IMMR_ADDRESS_RESET_VALUE           0x047101a8/* define the decrementer input clock frequency */#define DEC_CLOCK_FREQ	FREQ_66_MHZ/* define system clock rate *//* Internal Memory Map base Address */#define INTERNAL_MEM_MAP_ADDR		(IMMR_ADDRESS_RESET_VALUE & 0xfffe0000)	#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes *//* 8260pc *//* Latch base address */#define	LATCH_BASE_ADDR	0x04500000	/* Latch base address */#define LATCH_SIZE	0x00010000 /* Latch size */#ifdef _ASMLANGUAGE#define LATCH		LATCH_BASE_ADDR 		/* Register 0 */#else#define LATCH		((char *) (LATCH_BASE_ADDR))		/* Register 0 */#endif	/* _ASMLANGUAGE *//* 8260pc *//* LATCH bit definition (active at low level when _L) *//* By default, Fast Ethernet Enable is controlled by PC8 (R18 is soldered and R21 is desoldered) 			*//* It can be controlled by FETHEN#, bit 0 of latch by soldering R21 and desoldering R18	  						*//* If PC8 and FETHEN# are not initialized, Realtek 8201L is enabled as ISOLATE# is pulled down by R16	*//*0 1 2 3 4 5 6 7 | | | | | | | `----- 0x01 LATCH_SIG_LED1_L     	Signal LED 1 (red)| | | | | | `------- 0x02 LATCH_SIG_LED0_L     	Signal LED 0 (green)| | | | | `--------- 0x04 											reserved| | | | `----------- 0x08 											reserved| | | `------------- 0x10 											reserved| | `--------------- 0x20 											reserved| `----------------- 0x40 											reserved`------------------- 0x80 LATCH_FETHEN_L    	 	Fast Ethernet Enable  */#define LATCH_SIG_LED1_L	0x01	/* LED 1 */#define LATCH_LED_RED		LATCH_SIG_LED1_L#define LATCH_SIG_LED0_L	0x02	/* LED 0 */#define LATCH_LED_GREEN		LATCH_SIG_LED0_L#define LATCH_LED_ON		0x1#define LATCH_LED_OFF		0x0#define LATCH_FETHEN_L	0x80	/* Fast Ethernet Enable *//* For ADS *//* LATCH bit definition (active at low level when _L) *//*0 1 2 3 4 5 6 7 8-31| | | | | | | |  `-- 0x00800000 through 0x00000001   reserved| | | | | | | `----- 0x01000000 LATCH_SIG_LED1_L     Signal LED 1 (red)| | | | | | `------- 0x02000000 LATCH_SIG_LED0_L     Signal LED 0 (green)| | | | | `--------- 0x04000000 LATCH_L2_CLEAR_L     L2 Cache Clear| | | | `----------- 0x08000000 LATCH_L2_LOCK_L      L2 Cache Lock| | | `------------- 0x10000000 LATCH_L2_FLUSH_L     L2 Cache Flush| | `--------------- 0x20000000 LATCH_L2_INHIBIT_L   L2 Cache Inhibit| `----------------- 0x40000000 LATCH_L2_SRST		`------------------- 0x80000000 LATCH_FETHEN_L       *//* #define LATCH_SIG_LED1_L	0x01000000 */	/* LED 1 *//* #define LATCH_LED_RED		LATCH_SIG_LED1_L *//* #define LATCH_SIG_LED0_L	0x02000000 */	/* LED 0 *//* #define LATCH_LED_GREEN		LATCH_SIG_LED0_L *//* #define LATCH_LED_ON		0x1 *//* #define LATCH_LED_OFF		0x0 *//* #define LATCH_L2_CLEAR_L	0x04000000 */	/* L2 Cache Clear *//* #define LATCH_L2_LOCK_L		0x08000000 */	/* L2 Cache Lock *//* #define LATCH_L2_FLUSH_L	0x10000000 */	/* L2 Cache Flush *//* #define LATCH_L2_INHIBIT_L	0x20000000 */	/* L2 Cache Inhibit *//* CPU type in the PVR */#define CPU_TYPE_860			0x0050		/* value for PPC860 */#define CPU_TYPE_8260			0xAAAA		/* value for PPC8260 */#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num *//*  * Maximum number of SCC channels to configure as SIOs. Note that this  * assumes sequential usage of SCCs.*/#define MAX_SCC_SIO_CHANS 2#endif /* INCads8260h */