/* m8260Cpm.h - Motorola PPC8260 Communication Processor Module header file *//* Copyright 1984-1999 Wind River Systems, Inc. *//*modification history--------------------01d,15jul99,ms_  fix to meet coding standards01c,20may99,cn   added more definitions.01b,14apr99,ms_  add macros to help use multiple SCCs01a,08apr99,cn 	 created from ppc860Cpm.h, 01f.*//* * This file contains constants of the Communication Processor Module (CPM) for * the Motorola MPC8260 PowerPC microcontroller. */#ifndef __INCm8260Cpmh#define __INCm8260Cpmh#ifdef __cplusplusextern "C" {#endif    /* device and channel structures */#ifdef  _ASMLANGUAGE#define CAST(x)#else /* _ASMLANGUAGE */typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */typedef volatile INT32 VINT32; /* volatile unsigned word */typedef volatile INT16 VINT16; /* volatile unsigned halfword */typedef volatile INT8 VINT8;   /* volatile unsigned byte */typedef volatile UINT32 VUINT32; /* volatile unsigned word */typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */#define CAST(x) (x)#endif  /* _ASMLANGUAGE */#ifdef	_ASMLANGUAGE#  define SMC_ADRS(reg)	(M8260SMC1_BASE + (reg * M8260SMC1_REG_OFFSET))#else#  define SMC_ADRS(reg)	((VCHAR *)M8260SMC1_BASE+(reg*M8260SMC1_REG_OFFSET))#endif	/* _ASMLANGUAGE *//* * MPC8260 internal register/memory map (section 17 of prelim. spec) * note that these are offsets from the value stored in the IMMR * register. Also note that in the MPC8260, the IMMR is not a special * purpose register, but it is memory mapped. */ /* General SIU registers */ /* SIU Module Configuration Register */#define M8260_SIUMCR(base)      (CAST(VUINT32 *)((base) + 0x10000)) /* Protection Ctrl */#define M8260_SYPCR(base)       (CAST(VUINT32 *)((base) + 0x10004)) /* Bus Configuration Register */#define M8260_BCR(base)         (CAST(VUINT32 *)((base) + 0x10024)) /* 60x Bus Arbiter Configuration Register */#define M8260_PPC_ACR(base)     (CAST(VUINT32 *)((base) + 0x10028)) /* 60x Bus Arbitration Level Register High */#define M8260_PPC_ALRH(base)    (CAST(VUINT32 *)((base) + 0x1002c))#define M8260_PPC_ALRL(base)	(CAST(VUINT32 *)((base) +0x10030)) /* 60x Bus Transfer Error Control Status */#define M8260_TESCR1(base)      (CAST(VUINT32 *)((base) + 0x10040)) /* Local Bus Transfer Error Control Status */#define M8260_LTESCR1(base)     (CAST(VUINT32 *)((base) + 0x10048)) /* SW Service Reg */#define M8260_SWSR(base)        (CAST(VUINT16 *)((base) + 0x1000E)) #define SIPEND(base)    (CAST(VUINT32 *)((base) + 0x0010)) /* Intr Pending reg*/#define SIMASK(base)    (CAST(VUINT32 *)((base) + 0x0014)) /* Intr Mask reg */#define SIEL(base)      (CAST(VUINT32 *)((base) + 0x0018)) /* Intr Edge Lvl */#define SIVEC(base)     (CAST(VUINT32 *)((base) + 0x001C)) /* Intr Vector reg */#define TESR(base)      (CAST(VUINT32 *)((base) + 0x0020)) /* Tx Error Status */#define SDCR(base)      (CAST(VUINT32 *)((base) + 0x0030)) /* SDMA Config Reg */ /*  * MEMC registers  * The memory controller is part of the CPM */ /* Base Reg bank 0*/#define M8260_BR0(base)         (CAST(VUINT32 *)((base) + 0x10100))/* Opt Reg bank 0*/#define M8260_OR0(base)         (CAST(VUINT32 *)((base) + 0x10104))/* Base Reg bank 1*/#define M8260_BR1(base)         (CAST(VUINT32 *)((base) + 0x10108))/* Opt Reg bank 1*/#define M8260_OR1(base)         (CAST(VUINT32 *)((base) + 0x1010c))/* Base Reg bank 2*/#define M8260_BR2(base)         (CAST(VUINT32 *)((base) + 0x10110))/* Opt Reg bank 2*/#define M8260_OR2(base)         (CAST(VUINT32 *)((base) + 0x10114))/* Base Reg bank 3*/#define M8260_BR3(base)         (CAST(VUINT32 *)((base) + 0x10118))/* Opt Reg bank 3*/#define M8260_OR3(base)         (CAST(VUINT32 *)((base) + 0x1011c))/* Base Reg bank 4*/#define M8260_BR4(base)         (CAST(VUINT32 *)((base) + 0x10120))/* Opt Reg bank 4*/#define M8260_OR4(base)         (CAST(VUINT32 *)((base) + 0x10124))/* Base Reg bank 5*/#define M8260_BR5(base)         (CAST(VUINT32 *)((base) + 0x10128))/* Opt Reg bank 5*/#define M8260_OR5(base)         (CAST(VUINT32 *)((base) + 0x1012c))/* Base Reg bank 6*/#define M8260_BR6(base)         (CAST(VUINT32 *)((base) + 0x10130))/* Opt Reg bank 6*/#define M8260_OR6(base)         (CAST(VUINT32 *)((base) + 0x10134))/* Base Reg bank 7*/#define M8260_BR7(base)         (CAST(VUINT32 *)((base) + 0x10138))/* Opt Reg bank 7*/#define M8260_OR7(base)         (CAST(VUINT32 *)((base) + 0x1013c))/* Base Reg bank 8*/#define M8260_BR8(base)         (CAST(VUINT32 *)((base) + 0x10140))/* Opt Reg bank 8*/#define M8260_OR8(base)         (CAST(VUINT32 *)((base) + 0x10144))/* Base Reg bank 9*/#define M8260_BR9(base)         (CAST(VUINT32 *)((base) + 0x10148))/* Opt Reg bank 9*/#define M8260_OR9(base)         (CAST(VUINT32 *)((base) + 0x1014c))/* Base Reg bank 10*/#define M8260_BR10(base)        (CAST(VUINT32 *)((base) + 0x10150))/* Opt Reg bank 10*/#define M8260_OR10(base)        (CAST(VUINT32 *)((base) + 0x10154))/* Base Reg bank 11*/#define M8260_BR11(base)        (CAST(VUINT32 *)((base) + 0x10158))/* Opt Reg bank 11*/#define M8260_OR11(base)        (CAST(VUINT32 *)((base) + 0x1015c)) #define MAR(base)       (CAST(VUINT32 *)((base) + 0x10168)) /* Memory Address */#define MBMR(base)      (CAST(VUINT32 *)((base) + 0x10174)) /* Machine B Mode */#define MSTAT(base)     (CAST(VUINT16 *)((base) + 0x0178))  /* Memory Status *//* Mem Timer Presc*/#define M8260_MPTPR(base)       (CAST(VUINT16 *)((base) + 0x10184)) /* SDRAM refresh timer */#define M8260_PSRT(base)        (CAST(VUINT16 *)((base) + 0x1019c)) /* 60x bus SDRAM mode register */#define M8260_PSDMR(base)       (CAST(VUINT16 *)((base) + 0x10190)) #define MDR(base)       (CAST(VUINT32 *)((base) + 0x10188)) /* Memory Data */ /* Clock and Reset */ /* System Clk Ctrl */#define M8260_SCCR(base)        (CAST(VUINT32 *)((base) + 0x10c80)) #define M8260_CMXSI1CR(base)    (CAST(VUINT32 *) ((base) + 0x011B00))#define M8260_CMXSI2CR(base)    (CAST(VUINT32 *) ((base) + 0x011B02))#define M8260_CMXSMR(base)      (CAST(VUINT32 *) ((base) + 0x011B0C))#define M8260_CMXUAR(base)      (CAST(VUINT32 *) ((base) + 0x011B0E)) /* System Protection Control register bit definition (SYPCR - 0x04) */#define M8260_SYPCR_SWTC        0xffff0000      /* Software 'dog Timer Count */#define M8260_SYPCR_BMT         0x0000ff00      /* Bus Monitor Timing */#define M8260_SYPCR_PBME        0x00000080      /* 60x Bus Monitor Enable */#define M8260_SYPCR_LBME        0x00000040      /* local Bus Monitor Enable */#define M8260_SYPCR_SWE         0x00000004      /* Software Watchdog Enable */#define M8260_SYPCR_SWRI        0x00000002      /* Software Watchdog Reset/Int*/#define M8260_SYPCR_SWP         0x00000001      /* Software Watchdog Prescale */ /* Base Register bit definition */ #define M8260_BR_BA_MSK         0xffff8000      /* Base Address Mask */#define M8260_BR_RES_MSK        0x00006000      /* reserved field Mask */#define M8260_BR_PS_MSK         0x00001800      /* Port Size Mask */#define M8260_BR_PS_8           0x00000800      /* 8 bit port size */#define M8260_BR_PS_16          0x00001000      /* 16 bit port size */#define M8260_BR_PS_32          0x00001800      /* 32 bit port size */#define M8260_BR_PS_64          0x00000000      /* 64 bit port size */#define M8260_BR_DECC_MSK       0x00000600      /* data error checking */#define M8260_BR_DECC_DIS       0x00000000      /* error checking disabled */#define M8260_BR_DECC_NOR       0x00000200      /* normal parity checking */#define M8260_BR_DECC_RMW       0x00000400      /* RMW parity checking */#define M8260_BR_DECC_ECC       0x00000600      /* ECC checking */#define M8260_BR_WP             0x00000100      /* Write Protect */#define M8260_BR_MS_MSK         0x000000e0      /* Machine Select Mask */#define M8260_BR_MS_GPCM_60X    0x00000000      /* G.P.C.M. 60x Bus Machine */#define M8260_BR_MS_GPCM_LOC    0x00000020      /* G.P.C.M. Local Bus Machine */#define M8260_BR_MS_SDRAM_60X   0x00000040      /* SDRAM 60x Bus Machine */#define M8260_BR_MS_SDRAM_LOC   0x00000060      /* SDRAM Local Bus Machine */#define M8260_BR_MS_UPMA        0x00000080      /* U.P.M.A Machine */#define M8260_BR_MS_UPMB        0x000000a0      /* U.P.M.B Machine */#define M8260_BR_MS_UPMC        0x000000c0      /* U.P.M.C Machine */#define M8260_BR_EMEMC          0x00000010      /* External Memory Controller */#define M8260_BR_ATOM_MSK       0x0000000c      /* Atomic Operation Mask */#define M8260_BR_ATOM_NOT       0x00000000      /* No Atomic Operation */#define M8260_BR_ATOM_RAWA      0x00000004      /* RAWA Atomic Operation */#define M8260_BR_ATOM_WARA      0x00000008      /* WARA Atomic Operation */#define M8260_BR_DR             0x00000002      /* Data Pipelining */#define M8260_BR_V              0x00000001      /* Bank Valid */ /* Option Register bit definition */ #define M8260_OR_AM_MSK         0xffff8000      /* Address Mask Mask */#define M8260_OR_BCTLD          0x00001000      /* Data Buffer Control Disable*/#define M8260_OR_CSNT_EARLY     0x00000800      /* Chip Select Negation Time */#define M8260_OR_ACS_MSK        0x00000600      /* Addr to Chip Select Setup */#define M8260_OR_ACS_DIV1       0x00000000      /* CS output at the same time */#define M8260_OR_ACS_DIV4       0x00000400      /* CS output 1/4 clock later */#define M8260_OR_ACS_DIV2       0x00000600      /* CS output 1/2 clock later */