/*****************************************************************************
(C) Copyright 1999;  Tundra Semiconductor Corp.
*****************************************************************************/

/*----------------------------------------------------------------------------
* FILENAME: pspan.h
*
* DESCRIPTION:   
*
* Contains the PowerSpan-specific definitions.
*
* HISTORY:
*
*	Rev. Date       Author  Description
*	---- ---------  ------  ----------------------------------------------------
* 1.00 Aug.13,99  pg      Initial creation.
* 1.01 Aug.16,99  avb     Added type definitions for the PS_PCI_CONFIG,
*                         PCI_TARGET_IMAGE, PB_SLAVE_IMAGE and PS_DMA_CHANNEL.
*                         Modified PSPAN to use these definitions.
*                         Renamed some bitmasks.
* 1.02 Sep.21,99  avb     Added type definitions PCI_REGISTERS and PS_DMA_CP.
*
*---------------------------------------------------------------------------*/

#ifndef _PSPAN_H_
#define _PSPAN_H_

/*
 * PowerSpan PCI Configuration Registers
 */
typedef struct _ps_pci_config {
  VUINT32 id;        /* PCI ID Register */
  VUINT32 csr;       /* PCI Control and Status Register */
  VUINT32 pci_class; /* PCI Class Register */
  VUINT32 misc0;     /* PCI Miscellaneous 0 Register */
  VUINT32 bsi2o;     /* PCI I2O Target Image Base Address Register */
  VUINT32 bsreg;     /* PCI Register Image Base Address Register */
  VUINT32 bst[4];    /* PCI Target Images 0..3 Base Address Register */
  UINT8 RESERVED1[4];
  VUINT32 sid;       /* PCI Subsystem ID Register */
  UINT8 RESERVED2[4];
  VUINT32 cap;       /* PCI Capability Pointer Register */
  UINT8 RESERVED3[4];
  VUINT32 misc1;     /* PCI Miscellaneous 1 Register */
  UINT8 RESERVED4[164];
  VUINT32 hs_csr;    /* PCI cPCI Hot Swap Control and Status Register */
  VUINT32 vpdc;      /* PCI Vital Product Data Capability Register */
  VUINT32 vpdd;      /* PCI Vital Product Data Data Register */
  UINT8 RESERVED5[16];
} PS_PCI_CONFIG, *PPS_PCI_CONFIG;


/*
 * PCIx Target Image Registers
 */
typedef struct _pci_target_image {
  VUINT32 ctl;   /* PCI Target Image Control Register */
  VUINT32 taddr; /* PCI Target Image Translation Address Register */
  UINT8 RESERVED1[8];
} PCI_TARGET_IMAGE, *PPCI_TARGET_IMAGE;


/*
 * PCI n Registers 
 */
typedef struct _pci_registers {
  PCI_TARGET_IMAGE  ti[4]; /* PCI Target Images 0 - 3 */
  UINT8 RESERVED1[4];
  VUINT32 conf_info;    /* Configuration Cycle Information Reg */
  VUINT32 conf_data;    /* Configuration Cycle Data Register */
  VUINT32 iack;         /* Interrupt Ack Cycle Generation Reg */
  VUINT32 errcs;        /* Bus Error Control and Status Register */
  VUINT32 aerr;         /* Address Error Log Register */
  UINT8 RESERVED2[8];
  VUINT32 misc_csr;     /* Miscellaneous Control and Status Reg */
  VUINT32 arb_ctrl;     /* Bus Arbiter Control Register */
  UINT8 RESERVED3[152];
} PCI_REGISTERS, *PPCI_REGISTERS;

/*
 * Processor Bus Slave Image Registers
 */
typedef struct _pb_slave_image {
  VUINT32 ctl;    /* PB Slave Image Control Register */
  VUINT32 taddr;  /* PB Slave Image Translation Address Register */
  VUINT32 baddr;  /* PB Slave Image Base Address Register */
  UINT8 RESERVED1[4];
} PB_SLAVE_IMAGE, *PPB_SLAVE_IMAGE;


/*
 * PowerSpan DMA Channel Registers
 */
typedef struct _ps_dma_channel {
  UINT8 RESERVED1[4];
  VUINT32 src_addr;   /* DMAx Source Address Register */
  UINT8 RESERVED2[4];
  VUINT32 dst_addr;   /* DMAx Destination Address Register */
  UINT8 RESERVED3[4];
  VUINT32 tcr;        /* DMAx Transfer Control Register */
  UINT8 RESERVED4[4];
  VUINT32 cpp;        /* DMAx Command Packet Pointer Register */
  VUINT32 gcsr;       /* DMAx General Control Register */
  VUINT32 attr;       /* DMAx Attributes Register */
  UINT8 RESERVED5[8];
} PS_DMA_CHANNEL, *PPS_DMA_CHANNEL;


/*
 * Linked List DMA Command Packet.
 */
typedef struct _PS_DMA_CP
{
  VUINT32 RESERVED1;
  VUINT32 dma_src_addr;
  VUINT32 RESERVED2;
  VUINT32 dma_dst_addr;
  VUINT32 RESERVED3;
  VUINT32 dma_tcr;
  VUINT32 RESERVED4;
  VUINT32 dma_cpp;      /* pointer to the text element in the linked list */
} PS_DMA_CP, *PPS_DMA_CP;


/*
 * ##### PowerSpan ######
 */
typedef struct _pspan {

  /*
   * PCI 1 Configuration Registers
   */
  PS_PCI_CONFIG p1_cfg;

  /*
   * PCI 1 Registers
   */
  PCI_REGISTERS p1;

  /*
   * Processor Bus Registers
   */
  PB_SLAVE_IMAGE  pb_si[8]; /* PB Slave Images 0 - 7 */
  VUINT32 pb_reg_baddr; /* PB Register Image Base Address Register */
  UINT8 RESERVED1[12];
  VUINT32 pb_conf_info; /* PB PCI Configuration Cycle Information Reg */
  VUINT32 pb_conf_data; /* PB PCI Configuration Cycle Data Register */
  UINT8 RESERVED2[8];
  VUINT32 pb_p1_iack;   /* PB to PCI 1 Interrupt Ack Cycle Generation Reg */
  VUINT32 pb_p2_iack;   /* PB to PCI 2 Interrupt Ack Cycle Generation Reg */
  UINT8 RESERVED3[8];
  VUINT32 pb_errcs;     /* PB Error Control and Status Register */
  VUINT32 pb_aerr;      /* PB Address Error Log Register */
  UINT8 RESERVED4[8];
  VUINT32 pb_misc_csr;  /* PB Miscellaneous Control and Status Register */
  UINT8 RESERVED5[12];
  VUINT32 pb_arb_ctrl;  /* PB Arbiter Control Register */
  UINT8 RESERVED6[44];

  /*
   * DMA Registers
   */
  PS_DMA_CHANNEL  dma[4]; /* DMA Channels 0 - 3 */
  UINT8 RESERVED7[64];

  /*
   * Miscellaneous Registers
   */
  VUINT32 misc_csr;     /* Miscellaneous Control and Status Register */
  VUINT32 clock_ctl;    /* Clock Control Register */
  VUINT32 i2c_csr;      /* I2C Interface Control and Status Register */
  VUINT32 rst_csr;      /* Reset Control and Status Register */
  VUINT32 isr0;         /* Interrupt Status Register 0 */
  VUINT32 isr1;         /* Interrupt Status Register 1 */
  VUINT32 ier0;         /* Interrupt Enable Register 0 */
  VUINT32 ier1;         /* Interrupt Enable Register 1 */
  VUINT32 imr_mbox;     /* Interrupt Map Register: Mailbox */
  VUINT32 imr_db;       /* Interrupt Map Register: Doorbell */
  VUINT32 imr_dma;      /* Interrupt Map Register: DMA */
  VUINT32 imr_hw;       /* Interrupt Map Register: Hardware */
  VUINT32 imr_p1;       /* Interrupt Map Register: P1 */
  VUINT32 imr_p2;       /* Interrupt Map Register: P2 */
  VUINT32 imr_pb;       /* Interrupt Map Register: PB */
  VUINT32 imr2_pb;      /* Interrupt Map Register Two: PB */
  VUINT32 imr_misc;     /* Interrupt Map Register: Miscellaneous */
  VUINT32 idr;          /* Interrupt Direction Register */
  UINT8 RESERVED8[8];
  VUINT32 mbox[8];      /* Mailbox Registers 0 - 7 */
  VUINT8  sema[8];      /* Semaphore Registers 0 - 7 */
  UINT8 RESERVED9[136];

  /*
   * I20 Registers
   */
  VUINT32 pci_ti2o_ctl; /* PCI I2O Target Image Control Register */
  VUINT32 pci_ti2o_taddr;/* PCI I2O Target Image Translation Address Reg */
  VUINT32 i2o_csr;      /* I2O Control and Status Register */
  VUINT32 i2o_queue_bs; /* I2O Queue Base Address Register */
  VUINT32 ifl_bot;      /* I2O Inbound Free List Bottom Pointer Register */
  VUINT32 ifl_top;      /* I2O Inbound Free List Top Pointer Register */
  VUINT32 ifl_top_inc;  /* I2O Inbound Free List Top Ptr Increment Reg */
  VUINT32 ipl_bot;      /* I2O Inbound Post List Bottom Pointer Register */
  VUINT32 ipl_bot_inc;  /* I2O Inbound Post List Bottom Ptr Increment Reg */
  VUINT32 ipl_top;      /* I2O Inbound Post List Top Pointer Register */
  VUINT32 ofl_bot;      /* I2O Outbound Free List Bottom Pointer Register */
  VUINT32 ofl_bot_inc;  /* I2O Outbound Free List Bottom Ptr Increment Reg */
  VUINT32 ofl_top;      /* I2O Outbound Free List Top Pointer Register */
  VUINT32 opl_bot;      /* I2O Outbound Post List Bottom Pointer Register */
  VUINT32 opl_top;      /* I2O Outbound Post List Top Pointer Register */
  VUINT32 opl_top_inc;  /* I2O Outbound Post List Top Ptr Increment Reg */
  VUINT32 host_oio;     /* I2O Host Outbound Index Offset Register */
  VUINT32 host_oia;     /* I2O Host Outbound Index Alias Register */
  VUINT32 iop_oi;       /* I2O IOP Outbound Index Register */
  VUINT32 iop_oi_inc;   /* I2O IOP Outbound Index Increment Register */
  UINT8 RESERVED10[688];

  /*
   * PCI 2 Configuration Registers
   */
  PS_PCI_CONFIG p2_cfg;

  /*
   * PCI 2 Registers
   */
  PCI_REGISTERS p2;

  UINT8 RESERVED11[1536];
} PSPAN, *PPSPAN;

/*
 * PCI ID Register
 */

#define PCI_ID_DID      0xFFFF0000    /* Device ID */
#define PCI_ID_VID      0x0000FFFF    /* Vendor ID */

#define PSPAN_PCI_ID    0x8260        /* PowerSpan PCI Device ID */
#define PSPAN2P_PCI_ID  0x8261        /* PowerSpan 2P PCI Device ID */

/*
 * PCI Control and Status Register
 */

#define PCI_CSR_D_PE    0x80000000    /* Detected Parity Error */
#define PCI_CSR_S_SERR  0x40000000    /* Signaled SERR# */
#define PCI_CSR_R_MA    0x20000000    /* Received Master Abort */
#define PCI_CSR_R_TA    0x10000000    /* Received Target Abort */
#define PCI_CSR_S_TA    0x08000000    /* Signaled Target Abort */
#define PCI_CSR_DEVSEL  0x06000000    /* Device Select Timing */
#define PCI_CSR_MDP_D   0x01000000    /* Master Data Parity Detected */
#define PCI_CSR_TFBBC   0x00800000    /* Target Fast Back to Back Capable */
#define PCI_CSR_DEV66   0x00200000    /* Device 66 MHz */
#define PCI_CSR_CAP_L   0x00100000    /* Capabilities List */
#define PCI_CSR_MFBBC   0x00000200    /* Master Fast Back to Back Enable */
#define PCI_CSR_SERR_EN 0x00000100    /* SERR# Enable */
#define PCI_CSR_WAIT    0x00000080    /* Wait Cycle Control */
#define PCI_CSR_PERESP  0x00000040    /* Parity Error Response */
#define PCI_CSR_VGAPS   0x00000020    /* VGA Palette Snoop */
#define PCI_CSR_MWI_EN  0x00000010    /* Memory Write and Invalidate Enable */
#define PCI_CSR_SC      0x00000008    /* Special Cycles */
#define PCI_CSR_BM      0x00000004    /* Bus Master */
#define PCI_CSR_MS      0x00000002    /* Memory Space */
#define PCI_CSR_IOS     0x00000001    /* IO Space */

/*
 * PCI Class Register
 */

#define PCI_CLASS_BASE  0xFF000000    /* Base Class Code */
#define PCI_CLASS_SUB   0x00FF0000    /* Sub Class Code */
#define PCI_CLASS_PROG  0x0000FF00    /* Programming Interface */
#define PCI_CLASS_RID   0x000000FF    /* Revision ID */

/*
 * PCI Miscellaneous 0 Register
 */

#define PCI_MISC0_BISTC 0x80000000    /* BIST Capable */
#define PCI_MISC0_SBIST 0x40000000    /* Start BIST */
#define PCI_MISC0_CCODE 0x0F000000    /* Completion Code */
#define PCI_MISC0_MFUNCT 0x00800000   /* Multifunction Device */
#define PCI_MISC0_LAYOUT 0x007F0000   /* Configuration Space Layout */
#define PCI_MISC0_LTIMER 0x0000FF00   /* Latency Timer */
#define PCI_MISC0_CLINE 0x0000000C    /* Cacheline Size */

/*
 * PCI I2O Target Image Base Address Register
 */

#define PCI_BSI2O_BA      0xFFFF0000  /* Base Address */
#define PCI_BSI2O_PRFTCH  0x00000008  /* Prefetchable */
#define PCI_BSI2O_TYPE    0x00000006  /* Type */
#define PCI_BSI2O_SPACE   0x00000001  /* PCI Bus Address Space */

/*
 * PCI Register Image Base Address Register
 */

#define PCI_BSREG_BA      0xFFFFF000  /* Base Address */
#define PCI_BSREG_PRFTCH  0x00000008  /* Prefetchable */
#define PCI_BSREG_TYPE    0x00000006  /* Type */
#define PCI_BSREG_SPACE   0x00000001  /* PCI Bus Address Space */

/*
 * PCI Target Image X Base Address Register
 */

#define PCI_BST_BA        0xFFFF0000  /* Base Address */
#define PCI_BST_PRFTCH    0x00000008  /* Prefetchable */
#define PCI_BST_TYPE      0x00000006  /* Type */
#define PCI_BST_SPACE     0x00000001  /* PCI Bus Address Space */

/*
 * PCI Subsystem ID Register
 */

#define PCI_SID_SID       0xFFFF0000  /* Subsystem ID */
#define PCI_SID_SVID      0x0000FFFF  /* Subsystem Vendor ID */

/*
 * PCI Capability Pointer Register
 */

#define PCI_CAP_CAP_PTR   0x000000FC  /* Capabilities Pointer */

/*
 * PCI Miscellaneous 1 Register
 */

#define PCI_MISC1_MAX_LAT   0xFF000000  /* Maximum Latency */
#define PCI_MISC1_MIN_GNT   0x00FF0000  /* Minimum Grant */
#define PCI_MISC1_INT_PIN1  0x00008000  /* Interrupt Pin (0) */
#define PCI_MISC1_INT_PIN2  0x00007F00  /* Interrupt Pin (1-7) */
#define PCI_MISC1_INT_LINE  0x000000FF  /* Interrupt Line */

/*
 * Compact PCI Hot Swap Control and Status Register