#define IR0_DB1         0x00000200  /* Doorbell Reg 1 Written to in IER Reg */
#define IR0_DB0         0x00000100  /* Doorbell Reg 0 Written to in IER Reg */
#define IR0_MBOX7       0x00000080  /* Set When Mailbox 7 is Written to */
#define IR0_MBOX6       0x00000040  /* Set When Mailbox 6 is Written to */
#define IR0_MBOX5       0x00000020  /* Set When Mailbox 5 is Written to */
#define IR0_MBOX4       0x00000010  /* Set When Mailbox 4 is Written to */
#define IR0_MBOX3       0x00000008  /* Set When Mailbox 3 is Written to */
#define IR0_MBOX2       0x00000004  /* Set When Mailbox 2 is Written to */
#define IR0_MBOX1       0x00000002  /* Set When Mailbox 1 is Written to */
#define IR0_MBOX0       0x00000001  /* Set When Mailbox 0 is Written to */

/*
 * Interrupt Status Register 1
 * Interrupt Enable Register 1
 */

#define IR1_ISR0_ACTV     0x80000000  /* Interrupt Status Bit is active in 
                                                        the ISR0 Register */
#define IR1_PB_P1_RETRY   0x08000000  /* PB Max Retry Error 
                                                        in PCI 1 Bus Cycle */
#define IR1_PB_P2_RETRY   0x04000000  /* PB Max Retry Error 
                                                        in PCI 2 Bus Cycle */
#define IR1_PB_PB_RETRY   0x02000000  /* PB Max Retry Error - PB to PB DMA */
#define IR1_PB_P1_ERR     0x00800000  /* PB I/F PB_TEA - PCI 1 Bus */
#define IR1_PB_P2_ERR     0x00400000  /* PB I/F PB_TEA - PCI 2 Bus */
#define IR1_PB_PB_ERR     0x00200000  /* PB Detected an Error
                                                      during PB to PB DMA */
#define IR1_PB_A_PAR      0x00100000  /* PB Address Parity Error Detected */
#define IR1_PB_P1_D_PAR   0x00080000  /* PB Data Parity Error - PCI 1 Bus */
#define IR1_PB_P2_D_PAR   0x00040000  /* PB Data Parity Error - PCI 2 Bus */
#define IR1_PB_PB_D_PAR   0x00020000  /* PB Data Parity Err - PB to PB DMA */
#define IR1_P2_P1_ERR     0x00008000  /* PCI 2 I/F Detected Err - PCI 1 Bus */
#define IR1_P2_PB_ERR     0x00004000  /* PCI 2 I/F Detected Error - PB */
#define IR1_P2_P2_ERR     0x00002000  /* PCI 2 I/F Detected Error
                                                            - P2 to P2 DMA */
#define IR1_P2_A_PAR      0x00001000  /* PCI 2 I/F Detected 
                                                       Address Parity Error */
#define IR1_P2_P1_RETRY   0x00000800  /* PCI 2 Master Too Many Retries
                                                            - PCI 1 Bus */
#define IR1_P2_PB_RETRY   0x00000400  /* PCI 2 Master Too Many Retries
                                                            - PB */
#define IR1_P2_P2_RETRY   0x00000200  /* PCI 2 Master Too Many Retries
                                                            - P2 to P2 DMA */
#define IR1_P1_P2_ERR     0x00000080  /* PCI 1 I/F Detected Err - PCI 2 Bus */
#define IR1_P1_PB_ERR     0x00000040  /* PCI 1 I/F Detected Error - PB */
#define IR1_P1_P1_ERR     0x00000020  /* PCI 1 I/F Detected Error
                                                      - P1 to P1 DMA */
#define IR1_P1_A_PAR      0x00000010  /* PCI 1 I/F Detected
                                                      Address Parity Error */
#define IR1_P1_P2_RETRY   0x00000008  /* PCI 1 Master Too Many Retries
                                                            - PCI 2 Bus */
#define IR1_P1_PB_RETRY   0x00000004  /* PCI 1 Master Too Many Retries - PB */
#define IR1_P1_P1_RETRY   0x00000002  /* PCI 1 Master Too Many Retries
                                                            - P1 to P1 DMA */

/*
 * Interrupt Map Register: Mailbox
 */

#define IMR_MBOX_MBOX7_MAP  0xE0000000  /* Map Mbox #7 to an Interrupt Pin */
#define IMR_MBOX_MBOX6_MAP  0x0E000000  /* Map Mbox #6 to an Interrupt Pin */
#define IMR_MBOX_MBOX5_MAP  0x00E00000  /* Map Mbox #5 to an Interrupt Pin */
#define IMR_MBOX_MBOX4_MAP  0x000E0000  /* Map Mbox #4 to an Interrupt Pin */
#define IMR_MBOX_MBOX3_MAP  0x0000E000  /* Map Mbox #3 to an Interrupt Pin */
#define IMR_MBOX_MBOX2_MAP  0x00000E00  /* Map Mbox #2 to an Interrupt Pin */
#define IMR_MBOX_MBOX1_MAP  0x000000E0  /* Map Mbox #1 to an Interrupt Pin */
#define IMR_MBOX_MBOX0_MAP  0x0000000E  /* Map Mbox #0 to an Interrupt Pin */

/*
 * Interrupt Map Register: Doorbell
 */

#define IMR_DB_DB7_MAP  0xE0000000  /* Map Doorbell #7 to an Interrupt Pin */
#define IMR_DB_DB6_MAP  0x0E000000  /* Map Doorbell #6 to an Interrupt Pin */
#define IMR_DB_DB5_MAP  0x00E00000  /* Map Doorbell #5 to an Interrupt Pin */
#define IMR_DB_DB4_MAP  0x000E0000  /* Map Doorbell #4 to an Interrupt Pin */
#define IMR_DB_DB3_MAP  0x0000E000  /* Map Doorbell #3 to an Interrupt Pin */
#define IMR_DB_DB2_MAP  0x00000E00  /* Map Doorbell #2 to an Interrupt Pin */
#define IMR_DB_DB1_MAP  0x000000E0  /* Map Doorbell #1 to an Interrupt Pin */
#define IMR_DB_DB0_MAP  0x0000000E  /* Map Doorbell #0 to an Interrupt Pin */

/*
 * Interrupt Map Register: DMA
 */

#define IMR_DMA_DMA3_MAP  0x0000E000  /* Map DMA #3 to an Interrupt Pin */
#define IMR_DMA_DMA2_MAP  0x00000E00  /* Map DMA #3 to an Interrupt Pin */
#define IMR_DMA_DMA1_MAP  0x000000E0  /* Map DMA #3 to an Interrupt Pin */
#define IMR_DMA_DMA0_MAP  0x0000000E  /* Map DMA #3 to an Interrupt Pin */

/*
 * Interrupt Map Register: Hardware
 */

#define IMR_HW_P2_HW_MAP    0xE0000000  /* Map P2 H/W Interrupt to Int. Pin */
#define IMR_HW_P1_HW_MAP    0x0E000000  /* Map P1 H/W Interrupt to Int. Pin */
#define IMR_HW_INT5_HW_MAP  0x00E00000  /* Map INT_[5] to Int. Pin */
#define IMR_HW_INT4_HW_MAP  0x000E0000  /* Map INT_[4] to Int. Pin */
#define IMR_HW_INT3_HW_MAP  0x0000E000  /* Map INT_[3] to Int. Pin */
#define IMR_HW_INT2_HW_MAP  0x00000E00  /* Map INT_[2] to Int. Pin */
#define IMR_HW_INT1_HW_MAP  0x000000E0  /* Map INT_[1] to Int. Pin */
#define IMR_HW_INT0_HW_MAP  0x0000000E  /* Map INT_[0] to Int. Pin */

/*
 * Interrupt Map Register: P1
 */

#define IMR_P1_P1_P2_ERR_MAP   0xE0000000 /* PCI 1 Errors to Int. Pin */
#define IMR_P1_P1_PB_ERR_MAP   0x0E000000 /* PCI 1 Errors to Int. Pin - PB */
#define IMR_P1_P1_P1_ERR_MAP   0x00E00000 /* PCI 1 Errors to Int. Pin
                                                    - P1 to P1 DMA */
#define IMR_P1_P1_A_PAR_MAP    0x000E0000 /* PCI 1 Address Parity Errors
                                                      to Int. Pin */
#define IMR_P1_P1_P2_RETRY_MAP 0x0000E000 /* PCI 1 Max Retry Error
                                                      to Int. Pin */
#define IMR_P1_P1_PB_RETRY_MAP 0x000000E0 /* PCI 1 Max Retry Error
                                                to Int. Pin - P1 to P1 DMA */
#define IMR_P1_P1_P1_RETRY_MAP 0x000000E0 /* PCI 1 Max Retry Error 
                                                to Int. Pin - P1 to P1 DMA */

/*
 * Interrupt Map Register: P2
 */

#define IMR_P2_P2_P1_ERR_MAP 0xE0000000    /* PCI 2 Error to Int. Pin */
#define IMR_P2_P2_PB_ERR_MAP 0x0E000000    /* PCI 2 Errors to Int. Pin */
#define IMR_P2_P2_P2_ERR_MAP 0x00E00000    /* PCI 2 Errors to Int. Pin
                                                      - P2 to P2 DMA */
#define IMR_P2_P2_A_PAR_MAP 0x000E0000     /* PCI 2 Address Parity Errors
                                                      to Int. Pin */
#define IMR_P2_P2_P1_RETRY_MAP 0x0000E000  /* PCI 2 Max Retry Error
                                                      to Int. Pin */
#define IMR_P2_P2_PB_RETRY_MAP 0x00000E00  /* PCI 2 Max Retry Error
                                                      to Int. Pin */
#define IMR_P2_P2_P2_RETRY_MAP 0x000000E0  /* PCI 2 Max Retry Error
                                                 to Int. Pin - P2 to P2 DMA */

/*
 * Interrupt Map Register: PB
 */

#define IMR_PB_PB_P1_ERR_MAP    0xE0000000  /* PB Error to Int. Pin */
#define IMR_PB_PB_P2_ERR_MAP    0x0E000000  /* PB Error to Int. Pin */
#define IMR_PB_PB_PB_ERR_MAP    0x00E00000  /* PB to PB DMA */
#define IMR_PB_PB_A_PAR_MAP     0x000E0000  /* PB Address Parity Error
                                                            to Int. Pin */
#define IMR_PB_PB_P1_D_PAR_MAP  0x0000E000  /* PB Data Bus Parity Error
                                                            to Int. Pin */
#define IMR_PB_PB_P2_D_PAR_MAP  0x00000E00  /* PB Data Bus Parity Error
                                                            to Int. Pin */
#define IMR_PB_PB_PB_D_PAR_MAP  0x000000E0  /* PB Data Bus Parity Error
                                                to Int. Pin - PB to PB DMA */

/*
 * Interrupt Map Register Two: PB
 */

#define IMR2_PB_PB_P1_RETRY_MAP 0xE0000000 /* Map PB Max Retry Errors */
#define IMR2_PB_PB_P2_RETRY_MAP 0x0E000000 /* Map PB Max Retry Errors */
#define IMR2_PB_PB_PB_RETRY_MAP 0x00E00000 /* Map PB Max Retry Errors */

/*
 * Interrupt Map Register: Miscellaneous
 */

#define IMR_MISC_I2O_IOP_MAP  0xE0000000  /* Map I2O Host Int. to Int. Pin */
#define IMR_MISC_I2O_HOST_MAP 0x0E000000  /* Map I2O IOP Int. to Int. Pin */

/*
 * Interrupt Direction Register
 */

#define IDR_P2_HW_DIR   0x80000000  /* P2_INTA Direction */
#define IDR_P1_HW_DIR   0x40000000  /* P1_INTA Direction */
#define IDR_INT5_HW_DIR 0x20000000  /* INT[5] Direction */
#define IDR_INT4_HW_DIR 0x10000000  /* INT[4] Direction */
#define IDR_INT3_HW_DIR 0x08000000  /* INT[3] Direction */
#define IDR_INT2_HW_DIR 0x04000000  /* INT[2] Direction */
#define IDR_INT1_HW_DIR 0x02000000  /* INT[1] Direction */
#define IDR_INT0_HW_DIR 0x01000000  /* INT[0] Direction */

/*
 * Semaphore Registers
 */

#define SEMA_SEM 0x80   /* Semaphore X */
#define SEMA_TAG 0x7F   /* Tag X */

/*
 * PCI I2O Target Image Control Register
 */

#define PCI_TI2O_CTL_IMG_EN 0x80000000  /* Image Enable */
#define PCI_TI2O_CTL_TA_EN  0x40000000  /* Translation Address Enable */
#define PCI_TI2O_CTL_BAR_EN 0x20000000  /* PCI Base Address Register Enable */
#define PCI_TI2O_CTL_BS     0x0F000000  /* Block Size */
#define PCI_TI2O_CTL_RTT    0x001F0000  /* PB Read Transfer Type */
#define PCI_TI2O_CTL_GBL_   0x00008000  /* Global */
#define PCI_TI2O_CTL_CI_    0x00004000  /* Cache Inhibit */
#define PCI_TI2O_CTL_WTT    0x00001F00  /* PB Write Transfer Type */
#define PCI_TI2O_CTL_PRKEEP 0x00000080  /* Prefetch Read Keep Data */
#define PCI_TI2O_CTL_END    0x00000060  /* Endian Conversion Mode */
#define PCI_TI2O_CTL_MRA    0x00000010  /* PCI Memory Read Alias
                                            to Memory Read Multiple */
#define PCI_TI2O_CTL_RD_AMT 0x00000007  /* Prefetch Size */

/*
 * PCI I2O Target Image Translation Address Register
 */

#define PCI_TI2O_TADDR_TADDR  0xFFFF0000  /* Translation Address */

/*
 * I2O Control and Status Register
 */

#define I2O_CSR_HOPL_SIZE 0x000000E0  /* Host Outbound Post List Size */
#define I2O_CSR_EMTR      0x00000010  /* Empty FIFO Read Response */
#define I2O_CSR_OFL       0x00000008  /* Outbound Free List */
#define I2O_CSR_IPL       0x00000004  /* Inbound Post List */
#define I2O_CSR_XI2O_EN   0x00000002  /* Extended MFA Enabled */
#define I2O_CSR_I20_EN    0x00000001  /* I2O Enabled */

/*
 * I2O Queue Base Address Register
 */

#define I2O_QUEUE_BS_PB_I2O_BS 0xFFF00000  /* PB I2O Base Address */
#define I2O_QUEUE_BS_FIFO_SIZE 0x00000007  /* FIFO Size */

/*
 * I2O Inbound Free List Bottom Pointer Register
 */

#define IFL_BOT_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define IFL_BOT_BOT       0x000FFFFC  /* Inbound Free List Bottom Pointer */

/*
 * I2O Inbound Free List Top Pointer Register
 */

#define IFL_TOP_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define IFL_TOP_TOP       0x000FFFFC  /* Inbound Free List Top Pointer */

/*
 * I2O Inbound Free List Top Pointer Increment Register
 */

#define IFL_TOP_INC_INCR  0x00000001

/*
 * I2O Inbound Post List Bottom Pointer Register
 */

#define IPL_BOT_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define IPL_BOT_BOT       0x000FFFFC  /* Inbound Free List Bottom Pointer */

/*
 * I2O Inbound Post List Bottom Pointer Increment Register
 */

#define IPL_BOT_INC_INCR  0x00000001

/*
 * I2O Inbound Post List Top Pointer Register
 */

#define IPL_TOP_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define IPL_TOP_TOP       0x000FFFFC  /* Inbound Post List Top Pointer */

/*
 * I2O Outbound Free List Bottom Pointer Register
 */

#define OFL_BOT_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define OFL_BOT_BOT       0x000FFFFC  /* Outbound Free List Bottom Pointer */

/*
 * I2O Outbound Free List Bottom Pointer Increment Register
 */

#define OFL_BOT_INC_INCR 0x00000001

/*
 * I2O Outbound Free List Top Pointer Register
 */

#define OFL_TOP_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define OFL_TOP_TOP       0x000FFFFC  /* Outbound Free List Top Pointer */

/*
 * I2O Outbound Post List Bottom Pointer Register
 */

#define OPL_BOT_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define OPL_BOT_BOT       0x000FFFFC  /* Outbound Post List Bottom Pointer */

/*
 * I2O Outbound Post List Top Pointer Register
 */

#define OPL_TOP_PB_I2O_BS 0xFFF00000  /* Processor Bus I2O Base Address */
#define OPL_TOP_TOP       0x000FFFFC  /* Outbound Post List Top Pointer */

/*
 * I2O Outbound Post List Top Pointer Increment Register
 */

#define OPL_TOP_INC_INCR 0x00000001

/*
 * I2O Host Outbound Index Offset Register
 */

#define HOST_OIO_OIO  0x00000FFC  /* Host Outbound Index Offset */

/*
 * I2O Host Outbound Index Alias Register
 */

#define HOST_OIA_OIA  0xFFFFFFFC  /* Host Outbound Index Alias Register */

/*
 * I2O IOP Outbound Index Register
 */

#define IOP_OI_OI 0xFFFFFFFC      /* IOP Outbound Index */

/*
 * I2O IOP Outbound Index Increment Register
 */

#define IOP_OI_INC_INCR 0x00000001  /* IOP Outbound Index Increment */

#endif  /* _PSPAN_H_ */