/* motFccEnd.c - END style Motorola FCC Ethernet network interface driver *//* Copyright 1989-1998 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01e,15jul99,ms_  make compliant with our coding standards01d,16jun99,cn   added setting of MII_PHY_DEF_SET flag in motFccPhyPreInit ().01c,29apr99,ms_  added cache flush and invalidate routines01b,17apr99,cn   changed not to use zero-copy mode.01a,09apr99,cn   written from motFecEnd.c, 01c.*//*DESCRIPTIONThis module implements a Motorola Fast Communication Controller (FCC) Ethernet network interface driver. The FCC supports several communicationprotocols, and when progammed to operate in Ethernet mode, it is fully compliant with the IEEE 802.3u 10Base-T and 100Base-T specifications. The FCC establishes a shared memory communication system with the CPU,which may be divided into three parts: a set of Control/Status Registers (CSR)and FCC-specific parameters, the buffer descriptors (BD), and the data buffers. Both the CSRs and the internal parameters reside in the MPC8260's internal RAM. They are used for mode control and to extract status information of a global nature. For instance, the types of events that should generate an interrupt, or features like the promiscous mode or the hearthbeat control may be set programming some of the CSRs properly. Pointers to both the Transmit Buffer Descriptors ring (TBD) and theReceive Buffer Descriptors ring (RBD) are stored in the internal parameter RAM. The latter also includes protocol-specific parameters, like the individual physical address of this station or the max receive frame length.The BDs are used to pass data buffers and related buffer informationbetween the hardware and the software. They may reside either on the 60xbus, or on the CPM local bus They include local status information and a pointer to the incoming or outgoing data buffers. These are located again in external memory, and the user may chose whether this is on the 60x bus, or the CPM local bus (see below).This driver is designed to be moderately generic. Without modification, it canoperate across all the FCCs in the MPC8260, regardless of where the internal memory base address is located. To achieve this goal, this driver must be given several target-specific parameters, and some external support routines must be provided.  These parameters, and the mechanisms used to communicate them to the driver, are detailed below.This network interface driver does not include support for trailer protocolsor data chaining.  However, buffer loaning has been implemented in an effortto boost performance. In addition, no copy is performed of the outgoing packetbefore it is sent. BOARD LAYOUTThis device is on-board.  No jumpering diagram is necessary.EXTERNAL INTERFACEThe driver provides the standard external interface, motFccEndLoad(), whichtakes a string of colon-separated parameters. The parameters should bespecified in hexadecimal, optionally preceeded by "0x" or a minus sign "-".The parameter string is parsed using strtok_r() and each parameter isconverted from a string representation to binary by a call tostrtoul(parameter, NULL, 16).The format of the parameter string is:"<immrVal>:<fccNum>:<bdBase>:<bdSize>:<bufBase>:<bufSize>:<fifoTxBase>:<fifoRxBase> :<tbdNum>:<rbdNum>:<phyAddr>:<phyDefMode>:<userFlags>"TARGET-SPECIFIC PARAMETERS.IP <immrVal>Indicates the address at which the host processor presents its internal memory (also known as the internal RAM base address). With this address, and the fccNum (see below), the driver is able to compute the location of the FCC parameter RAM, and, ultimately, to program the FCC for proper operations. .IP <fccNum>This driver is written to support multiple individual device units.This parameter is used to explicitly state which FCC is being used (on thevads8260 board, FCC2 is wired to the Fast Ethernet tranceiver, thus this parameter equals "2")..IP <bdBase>The Motorola Fast Communication Controller is a DMA-type device and typically shares access to some region of memory with the CPU. This driver is designedfor systems that directly share memory between the CPU and the FCC.This parameter tells the driver that space for both the TBDs and the RBDs needs not be allocated but should be taken from a cache-coherent private memory space provided by the user at the given address. The user should be aware that memory used for buffers descriptors must be 8-byte aligned and non-cacheable. Therefore, the given memory space should allowfor all the buffer descriptors and the 8-byte alignment factor.If this parameter is "NONE", space for buffer descriptors is obtained by calling cacheDmaMalloc() in motFccEndLoad()..IP <bdSize>The memory size parameter specifies the size of the pre-allocated memoryregion for the BDs. If <bdBase> is specified as NONE (-1), the driver ignores this parameter. Otherwise, the driver checks the size of the provided memory region is adequate with respect to the given number of Transmit BufferDescriptors and Receive Buffer Descriptors..IP <bufBase>This parameter tells the driver that space for data buffersneeds not be allocated but should be taken from a cache-coherent private memory space provided by the user at the given address. The user should be aware that memory used for buffers must be 32-byte aligned and non-cacheable. The FCC poses one more constraint in that DMAcycles may initiate even when all the incoming data have already been transferred to memory. This means at most 32 bytes of memory at the end ofeach receive data buffer, may be overwritten during reception. The driverpads that area out, thus consuming some additional memory.If this parameter is "NONE", space for buffer descriptors is obtained by calling memalign() in motFccEndLoad()..IP <bufSize>The memory size parameter specifies the size of the pre-allocated memoryregion for data buffers. If <bufBase> is specified as NONE (-1), the driver ignores this parameter. Otherwise, the driver checks the size of the provided memory region is adequate with respect to the given number of Receive Buffer Descriptors and a non-configurable number of trasmit buffers (MOT_FCC_TX_CL_NUM).  All the above should fit in the given memory space. This area should also include room for buffer management structures..IP <fifoTxBase>Indicate the base location of the transmit FIFO, in internal memory.The user does not need to initialize this parameter, as the defaultvalue (see MOT_FCC_FIFO_TX_BASE) is highly optimized for best performance.However, if the user wishes to reserve that very area in internal RAM for other purposes, he may set this parameter to a different value. If <fifoTxBase> is specified as NONE (-1), the driver uses the defaultvalue..IP <fifoRxBase>Indicate the base location of the receive FIFO, in internal memory.The user does not need to initialize this parameter, as the defaultvalue (see MOT_FCC_FIFO_TX_BASE) is highly optimized for best performance.However, if the user wishes to reserve that very area in internal RAM for other purposes, he may set this parameter to a different value. If <fifoRxBase> is specified as NONE (-1), the driver uses the defaultvalue..IP <tbdNum>This parameter specifies the number of transmit buffer descriptors (TBDs). Each buffer descriptor resides in 8 bytes of the processor's externalRAM space, If this parameter is less than a minimum number specified in the macro MOT_FCC_TBD_MIN, or if it is "NULL", a default value of 64 (seeMOT_FCC_TBD_DEF_NUM) is used. This number is kept deliberately high, since each packet the driver sends may consume more than a single TBD. This parameter should always equal a even number..IP  <rbdNum>This parameter specifies the number of receive buffer descriptors (RBDs). Each buffer descriptor resides in 8 bytes of the processor's externalRAM space, and each one points to a 1584-byte buffer again in external RAM. If this parameter is less than a minimum number specified in the macro MOT_FCC_RBD_MIN, or if it is "NULL", a default value of 32 (seeMOT_FCC_RBD_DEF_NUM) is used. This parameter should always equal a even number..IP  <phyAddr>This parameter specifies the logical address of a MII-compliant physicaldevice (PHY) that is to be used as a physical media on the network.Valid addresses are in the range 0-31. There may be more than one deviceunder the control of the same management interface. The default physical layer initialization routine will scan the whole range of PHY devices starting from the one in <phyAddr>. If this parameter is "MII_PHY_NULL", the default physical layer initialization routine will find out the PHY actual address by scanning the whole range. The one with the lowestaddress will be chosen..IP  <phyDefMode>This parameter specifies the operating mode that will be set upby the default physical layer initialization routine in case allthe attempts made to establish a valid link failed. If that happens,the first PHY that matches the specified abilities will be chosen towork in that mode, and the physical link will not be tested. .IP  <pAnOrderTbl>This parameter may be set to the address of a table that specifies the order how different subsets of technology abilities should be advertised bythe auto-negotiation process, if enabled. Unless the flag <MOT_FCC_USR_PHY_TBL>is set in the userFlags field of the load string, the driver ignores thisparameter.The user does not normally need to specify this parameter, since the defaultbehaviour enables auto-negotiation process as described in IEEE 802.3u..IP  <userFlags>This field enables the user to give some degree of customization to thedriver. MOT_FCC_USR_PHY_NO_AN: the default physical layer initializationroutine will exploit the auto-negotiation mechanism as described inthe IEEE Std 802.3u, to bring a valid link up. According to it, allthe link partners on the media will take part to the negotiationprocess, and the highest priority common denominator technology abilitywill be chosen. It the user wishes to prevent auto-negotiation fromoccurring, he may set this bit in the user flags. MOT_FCC_USR_PHY_TBL: in the auto-negotiation process, PHYsadvertise all their technology abilities at the same time,and the result is that the maximum common denominator is used. However,this behaviour may be changed, and the user may affect the order howeach subset of PHY's abilities is negotiated. Hence, when theMOT_FCC_USR_PHY_TBL bit is set, the default physical layerinitialization routine will look at the motFccAnOrderTbl[] table andauto-negotiate a subset of abilities at a time, as suggested by thetable itself. It is worth noticing here, however, that if theMOT_FCC_USR_PHY_NO_AN bit is on, the above table will be ignored. MOT_FCC_USR_PHY_NO_FD: the PHY may be set to operate in full duplex mode,provided it has this ability, as a result of the negotiation with otherlink partners. However, in this operating mode, the FCC will ignore thecollision detect and carrier sense signals. If the user wishes not tonegotiate full duplex mode, he should set the MOT_FCC_USR_PHY_NO_FD bitin the user flags. MOT_FCC_USR_PHY_NO_HD: the PHY may be set to operate in half duplex mode,provided it has this ability, as a result of the negotiation with other linkpartners. If the user wishes not to negotiate half duplex mode, he shouldset the MOT_FCC_USR_PHY_NO_HD bit in the user flags. MOT_FCC_USR_PHY_NO_100: the PHY may be set to operate at 100Mbit/s speed,provided it has this ability, as a result of the negotiation withother link partners. If the user wishes not to negotiate 100Mbit/s speed,he should set the MOT_FCC_USR_PHY_NO_100 bit in the user flags. MOT_FCC_USR_PHY_NO_10: the PHY may be set to operate at 10Mbit/s speed,provided it has this ability, as a result of the negotiation withother link partners. If the user wishes not to negotiate 10Mbit/s speed,he should set the MOT_FCC_USR_PHY_NO_10 bit in the user flags. MOT_FCC_USR_PHY_ISO: some boards may have different PHYs controlled by thesame management interface. In some cases, there may be the need ofelectrically isolating some of them from the interface itself, in orderto guarantee a proper behaviour on the medium layer. If the user wishes toelectrically isolate all PHYs from the MII interface, he should set theMOT_FCC_USR_PHY_ISO bit. The default behaviour is to not isolate anyPHY on the board. MOT_FCC_USR_LOOP: when the MOT_FCC_USR_LOOP bit is set, the driver willconfigure the FCC to work in internal loopback mode, with the TX signal directly connected to the RX. This mode should only be used for testing. MOT_FCC_USR_RMON: when the MOT_FCC_USR_RMON bit is set, the driver willconfigure the FCC to work in RMON mode, thus collecting network statisticsrequired for RMON support without the need to receive all packets as inpromiscous mode. MOT_FCC_USR_BUF_LBUS: when the MOT_FCC_USR_BUF_LBUS bit is set, the driver willconfigure the FCC to work as though the data buffers were located in the CPM local bus.MOT_FCC_USR_BD_LBUS: when the MOT_FCC_USR_BD_LBUS bit is set, the driver willconfigure the FCC to work as though the buffer descriptors were located in the CPM local bus.MOT_FCC_USR_HBC: if the MOT_FCC_USR_HBC bit is set, the driver willconfigure the FCC to perform heartbeat check following end of transmissonand the HB bit in the status field of the TBD will be set if the collisioninput does not assert within the heartbeat window (also see _func_motFccHbFail,below). The user does not normally need to set this bit. .LPEXTERNAL SUPPORT REQUIREMENTSThis driver requires several external support functions:.IP sysFccEnetEnable().CS    STATUS sysFccEnetEnable (UINT32 immrVal, UINT8 fccNum);.CEThis routine is expected to handle any target-specific functions needed to enable the FCC. These functions typically include setting the Port B and Con the MPC8260 so that the MII interface may be used. This routine is expected to return OK on success, or ERROR. The driver calls this routine, once per device, from the motFccStart () routine..IP sysFccEnetDisable().CS    STATUS sysFccEnetDisable (UINT32 immrVal, UINT8 fccNum);.CEThis routine is expected to perform any target specific functions requiredto disable the MII interface to the FCC.  This involves restoring the default values for all the Port B and C signals. This routine is expected to return OK on success, or ERROR. The driver calls this routine from the motFccStop() routine each time a device is disabled..IP sysFccEnetAddrGet().CS    STATUS sysFccEnetAddrGet (UINT32 immrVal, UINT8 fccNum, UCHAR * enetAddr);.CEThe driver expects this routine to provide the six-byte Ethernet hardware address that is used by this device.  This routine must copy the six-byte address to the space provided by <enetAddr>.  This routine is expected to return OK on success, or ERROR.  The driver calls this routine, once per device, from the motFccEndLoad() routine..CS    STATUS sysFccMiiBitWr (UINT32 immrVal, UINT8 fccNum, INT32 bitVal);.CEThis routine is expected to perform any target specific functions requiredto write a single bit value to the MII management interface of a MII-compliantPHY device. The MII management interface is made up of two lines: management data clock (MDC) and management data input/output (MDIO). The former providesthe timing reference for transfer of information on the MDIO signal.The latter is used to transfer control and status information between thePHY and the FCC. For this transfer to be successful, the information itself has to be encoded into a frame format, and both the MDIO and MDC signals haveto comply with certain requirements as described in the 802.3u IEEE Standard.There is not buil-in support in the FCC for the MII management interface.This means that the clocking on the MDC line and the framing of the informationon the MDIO signal have to be done in software. Hence, this routine is expected to write the value in <bitVal> to the MDIO line while properly sourcing the MDC clock to a PHY, for one bit time..CS    STATUS sysFccMiiBitRd (UINT32 immrVal, UINT8 fccNum, INT8 * bitVal);.CEThis routine is expected to perform any target specific functions requiredto read a single bit value from the MII management interface of a MII-compliantPHY device. The MII management interface is made up of two lines: management data clock (MDC) and management data input/output (MDIO). The former providesthe timing reference for transfer of information on the MDIO signal.The latter is used to transfer control and status information between thePHY and the FCC. For this transfer to be successful, the information itself has to be encoded into a frame format, and both the MDIO and MDC signals haveto comply with certain requirements as described in the 802.3u IEEE Standard.There is not buil-in support in the FCC for the MII management interface.This means that the clocking on the MDC line and the framing of the informationon the MDIO signal have to be done in software. Hence, this routine is expected to read the value from the MDIO line in <bitVal>, while properly sourcing the MDC clock to a PHY, for one bit time..IP `_func_motFccPhyInit'.CS.IP `_func_motFccPhyInit'.CS    FUNCPTR _func_motFccPhyInit.CEThis driver sets the global variable `_func_motFccPhyInit' to the MII-compliant media initialization routine miiPhyInit(). If the user wishes to exploit a different way to configure the PHY, he may setthis variable to his own media initialization routine, tipicallyin sysHwInit()..IP `_func_motFccHbFail'.CS    FUNCPTR _func_motFccHbFail.CEThe FCC may be configured to perform heartbeat check following end of transmission, and to report any fealure in the relevant TBD status field. If this is the case, and if the global variable `_func_motFccHbFail'is not NULL, the routine referenced to by `_func_motFccHbFail' is called,with a pointer to the driver control structure as parameter. Hence,the user may set this variable to his own heart beat check fail routine,where he can take any action he sees appropriate.The default value for the global variable `_func_motFccHbFail' is NULL..LPSYSTEM RESOURCE USAGEIf the driver allocates the memory for the BDs to share with the FCC,it does so by calling the cacheDmaMalloc() routine.  For the default caseof 64 transmit buffers and 32 receive buffers, the total size requested is 776 bytes, and this includes the 8-byte alignment requirement of the device.  If a non-cacheable memory region is provided by the user, the size of this region should be this amount, unless the user has specified a different number of transmit or receive BDs. This driver can operate only if this memory region is non-cacheableor if the hardware implements bus snooping.  The driver cannot maintaincache coherency for the device because the BDs are asynchronouslymodified by both the driver and the device, and these fields share the same cache line.If the driver allocates the memory for the data buffers to share with the FCC,it does so by calling the memalign () routine.  The driver does not need touse cache-safe memory for data buffers, since the host CPU and the device arenot allowed to modify buffers asynchronously. The related cache linesare flushed or invalidated as appropriate. For the default caseof 7 transmit clusters and 32 receive clusters, the total size requested for this memory region is 112751 bytes, and this includes the 32-byte alignment and the 32-byte pad-out area per buffer of the device.  If a non-cacheable memory region is provided by the user, the size of this region should be this amount, unless the user has specified a different number of transmit or receive BDs. TUNING HINTS